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fx@3.10: finish Keyboard_Initialize, move CMT to another file

This commit is contained in:
Lephenixnoir 2020-03-03 10:21:28 +01:00
parent ec27f136b4
commit c6e2156e6e
5 changed files with 152 additions and 146 deletions
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20
asm/fx@3.10-%247.txt
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@ -29,9 +29,9 @@ Call graph:
%247 ==> <80056802> (reduction)
----------------------------------------------------------------------------
<80056802> GetKeyWait_Main
%aca setjmp (DONE)
%aca setjmp (DONE - Lephe)
<80089d8a> GetKeyWait_Dispatcher (STALLED - Lephe)
<80055d48> ? probably enables the keyboard interrupt
<80055d48> Keyboard_Initialize (DONE - Lephe)
<80057982> ?
<800578ba>
%420 OS_inner_Sleep
@ -88,8 +88,8 @@ Call graph:
Stack> (+4) (+0) || pr (x:u32) (&x) (+4) (+0)
# Tail-call <80056802> with a [u32 *] as an extra parameter. (The u32 itself
# is uninitialized, so it's probably an output.)
# Tail-call GetKeyWait_Main with a [u32 *] as an extra parameter. (The u32
# itself is uninitialized, so it's probably an output.)
800567e4: 4f22 sts.l pr, @-r15
800567e6: 7ffc add #-4, r15
800567e8: 61f3 mov r15, r1
@ -152,17 +152,15 @@ Call graph:
8005683e: 490b jsr @r9
80056840: 6403 mov r0, r4
# Do <80055d48> only if the KEYSC interrupt is disabled. From the looks of it
# this function enables that interrupt.
# According to Yatis, UCNTREG contains two fields: interrupt enable (bit 15)
# and some interrupt mode (bits 1-0). The OS probably uses only one value of
# the mode. That UCNTREG is checked as a boolean (thus ignoring the non-zero
# settings of bits 1-0) suggests that the OS always sets bits 1-0 to 0.
# If the KEYSC interrupt is disabled, initialize the whole keyboard (ports,
# KEYSC, interrupt, everything).
# The boolean test here and the UCNTREG setting in Keyboard_Initialize suggest
# that the OS always sets bits 1-0 of UCTNREG to 0.
80056842: d651 mov.l 0xa44b000c KEYSC.UCNTREG, r6
80056844: 6261 mov.w @r6, r2
80056846: 2228 tst r2, r2
80056848: 8b02 bf <80056850>
8005684a: d250 mov.l 0x80055d48, r2
8005684a: d250 mov.l 0x80055d48 Keyboard_Initialize, r2
8005684c: 420b jsr @r2
8005684e: 0009 nop

131
asm/fx@3.10/cmt.txt Normal file
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@ -0,0 +1,131 @@
<800540f6 CMT_InterruptiveSleep>
Performs a sleep using the CMT. If the CMT was previously running, it is
interrupted for the duration of the sleep then restored.
r4: Waiting delay. Each unit in r4 represents 1475 RCLK ticks. In the clock
mode 3 used by the OS, RCLK is input from the RTC_CLK at 32768 Hz, so the
delay will be about r4 * 45 ms.
r0: Always returns 1.
Stack> || r10 r11 r12 r13 r14 macl (*MSTPCR0) (r4)
# Store bit 0x4000 of MSTPCR0 (CMT power bit) to r6, then clear it.
# r1,r4,r11 will be a backup of the CMT state, initialize them to 0.
800540f6: 2fa6 mov.l r10, @-r15
800540f8: 2fb6 mov.l r11, @-r15
800540fa: 2fc6 mov.l r12, @-r15
800540fc: 2fd6 mov.l r13, @-r15
800540fe: 2fe6 mov.l r14, @-r15
80054100: 4f12 sts.l macl, @-r15
80054102: 7ff8 add #-8, r15
80054104: da2e mov.l 0xa4150030 POWER.MSTPCR0, r10
80054106: e340 mov #64, r3
80054108: eb00 mov #0, r11
8005410a: 4318 shll8 r3
8005410c: 2f42 mov.l r4, @r15
8005410e: 64b3 mov r11, r4
80054110: 61b3 mov r11, r1
80054112: de32 mov.l 0xa44a0060 CMT.CMCSR, r14
80054114: 67a2 mov.l @r10, r7
80054116: 1f71 mov.l r7, @(4,r15)
80054118: 2738 tst r3, r7
8005411a: 0029 movt r0
8005411c: dc30 mov.l 0xa44a0000 CMT.CMSTR, r12
8005411e: ca01 xor #1, r0
80054120: 62a2 mov.l @r10, r2
80054122: 954a mov.w 0xffffbfff, r5
80054124: 6603 mov r0, r6
80054126: 2259 and r5, r2
80054128: 2a22 mov.l r2, @r10
# If the CMT is running (bit #32 of CMSTR), stop it and save CMCSR, CMCOR and
# CMCNT to r11, r4 and r1.
8005412a: 60c1 mov.w @r12, r0
8005412c: c820 tst #32, r0
8005412e: 8d06 bt.s <8005413e>
80054130: 6db3 mov r11, r13
80054132: e700 mov #0, r7
80054134: 2c71 mov.w r7, @r12
80054136: 6be1 mov.w @r14, r11
80054138: ed01 mov #1, r13
8005413a: 54e2 mov.l @(8,r14), r4
8005413c: 51e1 mov.l @(4,r14), r1
# Stop the CMT. Wait for the CMCNT write flag to go down then set CMCSR=5.
# CMS=0 -> 32-bit counter
# CMM=0 -> One-shot mode
# CMR=0 -> No interrupt
# CKS=5 -> Counting at RCLK/32
8005413e: e720 mov #32, r7
80054140: e200 mov #0, r2
80054142: 2c21 mov.w r2, @r12
80054144: 4718 shll8 r7
80054146: 62e1 mov.w @r14, r2
80054148: 2278 tst r7, r2
8005414a: 8bfc bf <80054146>
8005414c: e505 mov #5, r5
8005414e: 2e51 mov.w r5, @r14
# Set CMCNT=0 and CMCOR=(1475*r4)/32, then start the CMT. (The CMCNT counts up
# and an overflow occurs when CMCNT=CMCOR.)
80054150: 65f2 mov.l @r15, r5
80054152: 9233 mov.w 0x000005c3, r2
80054154: e300 mov #0, r3
80054156: 1e31 mov.l r3, @(4,r14)
80054158: 0257 mul.l r5, r2
8005415a: 021a sts macl, r2
8005415c: e3fb mov #-5, r3
8005415e: d521 mov.l 0x00008000, r5
80054160: 423d shld r3, r2
80054162: 1e22 mov.l r2, @(8,r14)
80054164: 60c1 mov.w @r12, r0
80054166: cb20 or #32, r0
80054168: 2c01 mov.w r0, @r12
# Actively wait for the match flag to raise.
8005416a: 62e1 mov.w @r14, r2
8005416c: 622d extu.w r2, r2
8005416e: 2258 tst r5, r2
80054170: 89fb bt <8005416a>
# Stop the CMT. If it was running at the start of the function, wait again for
# the CMCNT write flag then restore CMCNT, CMCOR, CMCSR, and restart it.
80054172: 2dd8 tst r13, r13
80054174: e200 mov #0, r2
80054176: 8d0b bt.s <80054190>
80054178: 2c21 mov.w r2, @r12
8005417a: 62e1 mov.w @r14, r2
8005417c: 2278 tst r7, r2
8005417e: 8bfc bf <8005417a>
80054180: 951d mov.w 0xffffdfff, r5
80054182: 1e11 mov.l r1, @(4,r14)
80054184: 1e42 mov.l r4, @(8,r14)
80054186: 2b59 and r5, r11
80054188: 2eb1 mov.w r11, @r14
8005418a: 60c1 mov.w @r12, r0
8005418c: cb20 or #32, r0
8005418e: 2c01 mov.w r0, @r12
# If the CMT was not powered in MSTPCR0 initially, turn it back off.
80054190: 2668 tst r6, r6
80054192: 8904 bt <8005419e>
80054194: 62a2 mov.l @r10, r2
80054196: e140 mov #64, r1
80054198: 4118 shll8 r1
8005419a: 221b or r1, r2
8005419c: 2a22 mov.l r2, @r10
# Restore the stack and return 1.
8005419e: e001 mov #1, r0
800541a0: 7f08 add #8, r15
800541a2: 4f16 lds.l @r15+, macl
800541a4: 6ef6 mov.l @r15+, r14
800541a6: 6df6 mov.l @r15+, r13
800541a8: 6cf6 mov.l @r15+, r12
800541aa: 6bf6 mov.l @r15+, r11
800541ac: 000b rts
800541ae: 6af6 mov.l @r15+, r10
<800541b0 CMT_InterruptiveSleep>
800541b0: afa1 bra <800540f6>
800541b2: 0009 nop

140
asm/fx@3.10/kbd-config.txt
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@ -38,137 +38,6 @@
---
<800540f6 CMT_InterruptiveSleep>
Performs a sleep using the CMT. If the CMT was previously running, it is
interrupted for the duration of the sleep then restored.
r4: Waiting delay, in RCLK ticks (TODO: Frequency of RCLK)
r0: Always returns 1.
Stack> || r10 r11 r12 r13 r14 macl (*MSTPCR0) (r4)
# Store bit 0x4000 of MSTPCR0 (CMT power bit) to r6, then clear it.
# r1,r4,r11 will be a backup of the CMT state, initialize them to 0.
800540f6: 2fa6 mov.l r10, @-r15
800540f8: 2fb6 mov.l r11, @-r15
800540fa: 2fc6 mov.l r12, @-r15
800540fc: 2fd6 mov.l r13, @-r15
800540fe: 2fe6 mov.l r14, @-r15
80054100: 4f12 sts.l macl, @-r15
80054102: 7ff8 add #-8, r15
80054104: da2e mov.l 0xa4150030 POWER.MSTPCR0, r10
80054106: e340 mov #64, r3
80054108: eb00 mov #0, r11
8005410a: 4318 shll8 r3
8005410c: 2f42 mov.l r4, @r15
8005410e: 64b3 mov r11, r4
80054110: 61b3 mov r11, r1
80054112: de32 mov.l 0xa44a0060 CMT.CMCSR, r14
80054114: 67a2 mov.l @r10, r7
80054116: 1f71 mov.l r7, @(4,r15)
80054118: 2738 tst r3, r7
8005411a: 0029 movt r0
8005411c: dc30 mov.l 0xa44a0000 CMT.CMSTR, r12
8005411e: ca01 xor #1, r0
80054120: 62a2 mov.l @r10, r2
80054122: 954a mov.w 0xffffbfff, r5
80054124: 6603 mov r0, r6
80054126: 2259 and r5, r2
80054128: 2a22 mov.l r2, @r10
# If the CMT is running (bit #32 of CMSTR), stop it and save CMCSR, CMCOR and
# CMCNT to r11, r4 and r1.
8005412a: 60c1 mov.w @r12, r0
8005412c: c820 tst #32, r0
8005412e: 8d06 bt.s <8005413e>
80054130: 6db3 mov r11, r13
80054132: e700 mov #0, r7
80054134: 2c71 mov.w r7, @r12
80054136: 6be1 mov.w @r14, r11
80054138: ed01 mov #1, r13
8005413a: 54e2 mov.l @(8,r14), r4
8005413c: 51e1 mov.l @(4,r14), r1
# Stop the CMT. Wait for the CMCNT write flag to go down then set CMCSR=5.
# CMS=0 -> 32-bit counter
# CMM=0 -> One-shot mode
# CMR=0 -> No interrupt
# CKS=5 -> Counting at RCLK/32
8005413e: e720 mov #32, r7
80054140: e200 mov #0, r2
80054142: 2c21 mov.w r2, @r12
80054144: 4718 shll8 r7
80054146: 62e1 mov.w @r14, r2
80054148: 2278 tst r7, r2
8005414a: 8bfc bf <80054146>
8005414c: e505 mov #5, r5
8005414e: 2e51 mov.w r5, @r14
# Set CMCNT=0 and CMCOR=(1475*r4)/32, then start the CMT.
80054150: 65f2 mov.l @r15, r5
80054152: 9233 mov.w 0x000005c3, r2
80054154: e300 mov #0, r3
80054156: 1e31 mov.l r3, @(4,r14)
80054158: 0257 mul.l r5, r2
8005415a: 021a sts macl, r2
8005415c: e3fb mov #-5, r3
8005415e: d521 mov.l 0x00008000, r5
80054160: 423d shld r3, r2
80054162: 1e22 mov.l r2, @(8,r14)
80054164: 60c1 mov.w @r12, r0
80054166: cb20 or #32, r0
80054168: 2c01 mov.w r0, @r12
# Actively wait for the match flag to raise.
8005416a: 62e1 mov.w @r14, r2
8005416c: 622d extu.w r2, r2
8005416e: 2258 tst r5, r2
80054170: 89fb bt <8005416a>
# Stop the CMT. If it was running at the start of the function, wait again for
# the CMCNT write flag then restore CMCNT, CMCOR, CMCSR, and restart it.
80054172: 2dd8 tst r13, r13
80054174: e200 mov #0, r2
80054176: 8d0b bt.s <80054190>
80054178: 2c21 mov.w r2, @r12
8005417a: 62e1 mov.w @r14, r2
8005417c: 2278 tst r7, r2
8005417e: 8bfc bf <8005417a>
80054180: 951d mov.w 0xffffdfff, r5
80054182: 1e11 mov.l r1, @(4,r14)
80054184: 1e42 mov.l r4, @(8,r14)
80054186: 2b59 and r5, r11
80054188: 2eb1 mov.w r11, @r14
8005418a: 60c1 mov.w @r12, r0
8005418c: cb20 or #32, r0
8005418e: 2c01 mov.w r0, @r12
# If the CMT was not powered in MSTPCR0 initially, turn it back off.
80054190: 2668 tst r6, r6
80054192: 8904 bt <8005419e>
80054194: 62a2 mov.l @r10, r2
80054196: e140 mov #64, r1
80054198: 4118 shll8 r1
8005419a: 221b or r1, r2
8005419c: 2a22 mov.l r2, @r10
# Restore the stack and return 1.
8005419e: e001 mov #1, r0
800541a0: 7f08 add #8, r15
800541a2: 4f16 lds.l @r15+, macl
800541a4: 6ef6 mov.l @r15+, r14
800541a6: 6df6 mov.l @r15+, r13
800541a8: 6cf6 mov.l @r15+, r12
800541aa: 6bf6 mov.l @r15+, r11
800541ac: 000b rts
800541ae: 6af6 mov.l @r15+, r10
<800541b0 CMT_InterruptiveSleep>
800541b0: afa1 bra <800540f6>
800541b2: 0009 nop
---
<80055d36 Keyboard_ConfigurePorts>
Configures keyboard for low-level (and probably KEYSC) access. This has not
been fully documented to the best of my knowledge.
@ -189,7 +58,9 @@
80055d44: 000b rts
80055d46: 2261 mov.w r6, @r2
<80055d48>
<80055d48 Keyboard_Initialize>
Fully initializes the keyboard hardware: ports, KEYSC, interrupt. This
function has a long sleep built-in (45 ms), making it pretty slow.
# Stop the keyboard interrupt configuring and set the port parameters
80055d48: 4f22 sts.l pr, @-r15
@ -199,7 +70,7 @@
80055d50: bff1 bsr <80055d36 Keyboard_ConfigurePorts>
80055d52: e401 mov #1, r4
# Initialize the KEYSC configuration
# Initialize the KEYSC configuration then sleep for about 45 ms.
# UCNTREG = 0x8000
# UINTREG = 0x00ff
# UINTREG = 0x4800
@ -210,7 +81,6 @@
# OUTPINSET = 0x0fff
# INPINSET = 0x00ff
# UMODEREG = 0x0200
# <800541b0>(1)
80055d54: d53d mov.l 0xa44b000c KEYSC.UCNTREG, r5
80055d56: e2ff mov #-1, r2
80055d58: 622c extu.b r2, r2
@ -235,7 +105,7 @@
80055d7e: 901f mov.w 0x00000fff, r0
80055d80: 8157 mov.w r0, @(14,r5)
80055d82: 6023 mov r2, r0
80055d84: d132 mov.l 0x800541b0, r1
80055d84: d132 mov.l 0x800541b0 CMT_InterruptiveSleep, r1
80055d86: 8158 mov.w r0, @(16,r5)
80055d88: e002 mov #2, r0
80055d8a: 4018 shll8 r0

6
symbols/fx@3.10/cmt.txt Normal file
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@ -0,0 +1,6 @@
name: CMT
type: symbols
target: fx@3.10
---
800540f6 CMT_InterruptiveSleep

1
symbols/fx@3.10/kbd-config.txt
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@ -6,3 +6,4 @@ target: fx@3.10
80053a98 Keyboard_DisableInterrupt
80053aa0 Keyboard_EnableInterrupt
80055d36 Keyboard_ConfigurePorts
80055d48 Keyboard_Initialize