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[
{
"code": "0011nnnnmmmm1100",
"desc": "Rm,Rn",
"family": "ADD",
"name": "ADD",
"operands": "(long m, long n)",
"implementation": "ADD(long m, long n) /* ADD Rm,Rn */\r\n{\r\n R[n] += R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0111nnnniiiiiiii",
"desc": "#imm,Rn",
"family": "ADD",
"name": "ADDI",
"operands": "(long i, long n)",
"implementation": "ADDI(long i, long n) /* ADD #imm,Rn */\r\n{\r\n if ((i&0x80)==0)\r\n R[n] += (0x000000FF & (long)i);\r\n else R[n] += (0xFFFFFF00 | (long)i);\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1110",
"desc": "Rm,Rn",
"family": "ADDC",
"name": "ADDC",
"operands": "(long m, long n)",
"implementation": "ADDC(long m, long n) /* ADDC Rm,Rn */\r\n{\r\n unsigned long tmp0,tmp1;\r\n tmp1 = R[n] + R[m];\r\n tmp0 = R[n];\r\n R[n] = tmp1 + T;\r\n if (tmp0>tmp1) T = 1;\r\n else T = 0;\r\n if (tmp1>R[n]) T = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1111",
"desc": "Rm,Rn",
"family": "ADDV",
"name": "ADDV",
"operands": "(long m, long n)",
"implementation": "ADDV(long m, long n) /* ADDV Rm,Rn */\r\n{\r\n long dest,src,ans;\r\n if ((long)R[n]>=0) dest = 0;\r\n else dest = 1;\r\n if ((long)R[m]>=0) src = 0;\r\n else src = 1;\r\n src += dest;\r\n R[n] += R[m];\r\n if ((long)R[n]>=0) ans = 0;\r\n else ans = 1;\r\n ans += dest;\r\n if (src==0 || src==2) {\r\n if (ans==1) T = 1;\r\n else T = 0;\r\n }\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1001",
"desc": "Rm,Rn",
"family": "AND",
"name": "AND",
"operands": "(long m, long n)",
"implementation": "AND(long m, long n) /* AND Rm,Rn */\r\n{\r\n R[n] &= R[m];\r\n PC += 2;\r\n}"
},
{
"code": "11001001iiiiiiii",
"desc": "#imm,R0",
"family": "AND",
"name": "ANDI",
"operands": "(long i)",
"implementation": "ANDI(long i) /* AND #imm,R0 */\r\n{\r\n R[0] &= (0x000000FF & (long)i);\r\n PC += 2;\r\n}"
},
{
"code": "11001101iiiiiiii",
"desc": "#imm,@(R0,GBR)",
"family": "AND.B",
"name": "ANDM",
"operands": "(long i)",
"implementation": "ANDM(long i) /* AND.B #imm,@(R0,GBR) */\r\n{\r\n long temp;\r\n temp = (long)Read_Byte(GBR+R[0]);\r\n temp &= (0x000000FF & (long)i);\r\n Write_Byte(GBR+R[0],temp);\r\n PC += 2;\r\n}"
},
{
"code": "10001011dddddddd",
"desc": "label",
"family": "BF",
"name": "BF",
"operands": "(int d)",
"implementation": "BF(int d) /* BF disp */\r\n{\r\n int disp;\r\n if ((d&0x80)==0)\r\n disp = (0x000000FF & d);\r\n else disp = (0xFFFFFF00 | d);\r\n if (T==0)\r\n PC = PC+4+(disp<<1);\r\n else PC += 2;\r\n}"
},
{
"code": "10001111dddddddd",
"desc": "label",
"family": "BF/S",
"name": "BFS",
"operands": "(int d)",
"implementation": "BFS(int d) /* BFS disp */\r\n{\r\n int disp;\r\n unsigned int temp;\r\n temp = PC;\r\n if ((d&0x80)==0)\r\n disp = (0x000000FF & d);\r\n else disp = (0xFFFFFF00 | d);\r\n if (T==0)\r\n PC = PC + 4 + (disp<<1);\r\n else PC += 4;\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "1010dddddddddddd",
"desc": "label",
"family": "BRA",
"name": "BRA",
"operands": "(int d)",
"implementation": "BRA(int d) /* BRA disp */\r\n{\r\n int disp;\r\n unsigned int temp;\r\n temp = PC;\r\n if ((d&0x800)==0)\r\n disp = (0x00000FFF & d);\r\n else disp = (0xFFFFF000 | d);\r\n PC = PC + 4 + (disp<<1);\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0000nnnn00100011",
"desc": "Rn",
"family": "BRAF",
"name": "BRAF",
"operands": "(int n)",
"implementation": "BRAF(int n) /* BRAF Rn */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n PC = PC + 4 + R[n];\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "10001001dddddddd",
"desc": "label",
"family": "BT",
"name": "BT",
"operands": "(int d)",
"implementation": "BT(int d) /* BT disp */\r\n{\r\n int disp;\r\n if ((d&0x80)==0)\r\n disp = (0x000000FF & d);\r\n else disp = (0xFFFFFF00 | d);\r\n if (T==1)\r\n PC = PC + 4 + (disp<<1);\r\n else PC += 2;\r\n}"
},
{
"code": "10001101dddddddd",
"desc": "label",
"family": "BT/S",
"name": "BTS",
"operands": "(int d)",
"implementation": "BTS(int d) /* BTS disp */\r\n{\r\n int disp;\r\n unsigned temp;\r\n temp = PC;\r\n if ((d&0x80)==0)\r\n disp = (0x000000FF & d);\r\n else disp = (0xFFFFFF00 | d);\r\n if (T==1)\r\n PC = PC + 4 + (disp<<1);\r\n else PC += 4;\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0000000000101000",
"desc": "0",
"family": "CLRMAC",
"name": "CLRMAC",
"operands": "( )",
"implementation": "CLRMAC( ) /* CLRMAC */\r\n{\r\n MACH = 0;\r\n MACL = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0000000001001000",
"desc": "0",
"family": "CLRS",
"name": "CLRS",
"operands": "( )",
"implementation": "CLRS( ) /* CLRS */\r\n{\r\n S = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000001000",
"desc": "0",
"family": "CLRT",
"name": "CLRT",
"operands": "( )",
"implementation": "CLRT( ) /* CLRT */\r\n{\r\n T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0000",
"desc": "Rm,Rn",
"family": "CMP/EQ",
"name": "CMPEQ",
"operands": "(long m, long n)",
"implementation": "CMPEQ(long m, long n) /* CMP_EQ Rm,Rn */\r\n{\r\n if (R[n]==R[m]) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0011",
"desc": "Rm,Rn",
"family": "CMP/GE",
"name": "CMPGE",
"operands": "(long m, long n)",
"implementation": "CMPGE(long m, long n) /* CMP_GE Rm,Rn */\r\n{\r\n if ((long)R[n]>=(long)R[m]) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0111",
"desc": "Rm,Rn",
"family": "CMP/GT",
"name": "CMPGT",
"operands": "(long m, long n)",
"implementation": "CMPGT(long m, long n) /* CMP_GT Rm,Rn */\r\n{\r\n if ((long)R[n]>(long)R[m]) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0110",
"desc": "Rm,Rn",
"family": "CMP/HI",
"name": "CMPHI",
"operands": "(long m, long n)",
"implementation": "CMPHI(long m, long n) /* CMP_HI Rm,Rn */\r\n{\r\n if ((unsigned long)R[n]>(unsigned long)R[m]) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0010",
"desc": "Rm,Rn",
"family": "CMP/HS",
"name": "CMPHS",
"operands": "(long m, long n)",
"implementation": "CMPHS(long m, long n) /* CMP_HS Rm,Rn */\r\n{\r\n if ((unsigned long)R[n]>=(unsigned long)R[m]) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00010101",
"desc": "Rn",
"family": "CMP/PL",
"name": "CMPPL",
"operands": "(long n)",
"implementation": "CMPPL(long n) /* CMP_PL Rn */\r\n{\r\n if ((long)R[n]>0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00010001",
"desc": "Rn",
"family": "CMP/PZ",
"name": "CMPPZ",
"operands": "(long n)",
"implementation": "CMPPZ(long n) /* CMP_PZ Rn */\r\n{\r\n if ((long)R[n]>=0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1100",
"desc": "Rm,Rn",
"family": "CMP/STR",
"name": "CMPSTR",
"operands": "(long m, long n)",
"implementation": "CMPSTR(long m, long n) /* CMP_STR Rm,Rn */\r\n{\r\n unsigned long temp;\r\n long HH,HL,LH,LL;\r\n temp=R[n]^R[m];\r\n HH = (temp & 0xFF000000) >> 24;\r\n HL = (temp & 0x00FF0000) >> 16;\r\n LH = (temp & 0x0000FF00) >> 8;\r\n LL = temp & 0x000000FF;\r\n HH = HH && HL && LH && LL;\r\n if (HH==0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "10001000iiiiiiii",
"desc": "#imm,R0",
"family": "CMP/EQ",
"name": "CMPIM",
"operands": "(long i)",
"implementation": "CMPIM(long i) /* CMP_EQ #imm,R0 */\r\n{\r\n long imm;\r\n if ((i&0x80)==0) imm=(0x000000FF & (long) i);\r\n else imm=(0xFFFFFF00 | (long) i);\r\n if (R[0]==imm) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0111",
"desc": "Rm,Rn",
"family": "DIV0S",
"name": "DIV0S",
"operands": "(long m, long n)",
"implementation": "DIV0S(long m, long n) /* DIV0S Rm,Rn */\r\n{\r\n if ((R[n] & 0x80000000)==0) Q = 0;\r\n else Q = 1;\r\n if ((R[m] & 0x80000000)==0) M = 0;\r\n else M = 1;\r\n T = !(M==Q);\r\n PC += 2;\r\n}"
},
{
"code": "0000000000011001",
"desc": "0",
"family": "DIV0U",
"name": "DIV0U",
"operands": "( )",
"implementation": "DIV0U( ) /* DIV0U */\r\n{\r\n M = Q = T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm0100",
"desc": "Rm,Rn",
"family": "DIV1",
"name": "DIV1",
"operands": "(long m, long n)",
"implementation": "DIV1(long m, long n) /* DIV1 Rm,Rn */\r\n{\r\n unsigned long tmp0, tmp2;\r\n unsigned char old_q, tmp1;\r\n old_q = Q;\r\n Q = (unsigned char)((0x80000000 & R[n])!=0);\r\n tmp2 = R[m];\r\n R[n] <<= 1;\r\n R[n] |= (unsigned long)T;\r\n switch(old_q){\r\n case 0:switch(M){\r\n case 0:tmp0 = R[n];\r\n R[n] -= tmp2;\r\n tmp1 = (R[n]>tmp0);\r\n switch(Q){\r\n case 0:Q = tmp1;\r\n break;\r\n case 1:Q = (unsigned char)(tmp1==0);\r\n break;\r\n }\r\n break;\r\n case 1:tmp0 = R[n];\r\n R[n] += tmp2;\r\n tmp1 = (R[n]<tmp0);\r\n switch(Q){\r\n case 0:Q = (unsigned char)(tmp1==0);\r\n break;\r\n case 1:Q = tmp1;\r\n break;\r\n }\r\n break;\r\n }\r\n break;\r\n case 1:switch(M){\r\n case 0:tmp0 = R[n];\r\n R[n] += tmp2;\r\n tmp1 = (R[n]<tmp0);\r\n switch(Q){\r\n case 0:Q = tmp1;\r\n break;\r\n case 1:Q = (unsigned char)(tmp1==0);\r\n break;\r\n }\r\n break;\r\n case 1:tmp0 = R[n];\r\n R[n] -= tmp2;\r\n tmp1 = (R[n]>tmp0);\r\n switch(Q){\r\n case 0:Q = (unsigned char)(tmp1==0);\r\n break;\r\n case 1:Q = tmp1;\r\n break;\r\n }\r\n break;\r\n }\r\n break;\r\n }\r\n T = (Q==M);\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1101",
"desc": "Rm,Rn",
"family": "DMULS.L",
"name": "DMULS",
"operands": "(long m, long n)",
"implementation": "DMULS(long m, long n) /* DMULS.L Rm,Rn */\r\n{\r\n unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;\r\n unsigned long temp0,temp1,temp2,temp3;\r\n long tempm,tempn,fnLmL;\r\n tempn = (long)R[n];\r\n tempm = (long)R[m];\r\n if (tempn<0) tempn = 0 - tempn;\r\n if (tempm<0) tempm = 0 - tempm;\r\n if ((long)(R[n]^R[m])<0) fnLmL = -1;\r\n else fnLmL = 0;\r\n temp1 = (unsigned long)tempn;\r\n temp2 = (unsigned long)tempm;\r\n RnL = temp1&0x0000FFFF;\r\n RnH = (temp1>>16)&0x0000FFFF;\r\n RmL = temp2&0x0000FFFF;\r\n RmH = (temp2>>16)&0x0000FFFF;\r\n temp0 = RmL*RnL;\r\n temp1 = RmH*RnL;\r\n temp2 = RmL*RnH;\r\n temp3 = RmH*RnH;\r\n Res2 = 0;\r\n Res1 = temp1+temp2;\r\n if (Res1<temp1) Res2 += 0x00010000;\r\n temp1 = (Res1<<16)&0xFFFF0000;\r\n Res0 = temp0 + temp1;\r\n if (Res0<temp0) Res2++;\r\n Res2 = Res2 + ((Res1>>16)&0x0000FFFF) + temp3;\r\n if (fnLmL<0) {\r\n Res2 = ~\r\nRes2;\r\n if (Res0==0)\r\n Res2++;\r\n else\r\n Res0 = (~\r\nRes0) + 1;\r\n }\r\n MACH = Res2;\r\n MACL = Res0;\r\n PC +=2;\r\n }"
},
{
"code": "0011nnnnmmmm0101",
"desc": "Rm,Rn",
"family": "DMULU.L",
"name": "DMULU",
"operands": "(long m, long n)",
"implementation": "DMULU(long m, long n) /* DMULU.L Rm,Rn */\r\n{\r\n unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;\r\n unsigned long temp0,temp1,temp2,temp3;\r\n RnL = R[n] & 0x0000FFFF;\r\n RnH = (R[n]>>16) & 0x0000FFFF;\r\n RmL = R[m] & 0x0000FFFF;\r\n RmH = (R[m]>>16) & 0x0000FFFF;\r\n temp0 = RmL*RnL;\r\n temp1 = RmH*RnL;\r\n temp2 = RmL*RnH;\r\n temp3 = RmH*RnH;\r\n Res2 = 0;\r\n Res1 = temp1 + temp2;\r\n if (Res1<temp1) Res2 += 0x00010000;\r\n temp1 = (Res1<<16) & 0xFFFF0000;\r\n Res0 = temp0 + temp1;\r\n if (Res0<temp0) Res2++;\r\n Res2 = Res2 + ((Res1>>16)&0x0000FFFF) + temp3;\r\n MACH = Res2;\r\n MACL = Res0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00010000",
"desc": "Rn",
"family": "DT",
"name": "DT",
"operands": "(long n)",
"implementation": "DT(long n)/* DT Rn */\r\n{\r\n R[n]--;\r\n if (R[n]==0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1110",
"desc": "Rm,Rn",
"family": "EXTS.B",
"name": "EXTSB",
"operands": "(long m, long n)",
"implementation": "EXTSB(long m, long n) /* EXTS.B Rm,Rn */\r\n{\r\n R[n] = R[m];\r\n if ((R[m] & 0x00000080)==0) R[n] &=0x000000FF;\r\n else R[n] |= 0xFFFFFF00;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1111",
"desc": "Rm,Rn",
"family": "EXTS.W",
"name": "EXTSW",
"operands": "(long m, long n)",
"implementation": "EXTSW(long m, long n) /* EXTS.W Rm,Rn */\r\n{\r\n R[n] = R[m];\r\n if ((R[m] & 0x00008000)==0) R[n] &=0x0000FFFF;\r\n else R[n] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1100",
"desc": "Rm,Rn",
"family": "EXTU.B",
"name": "EXTUB",
"operands": "(long m, long n)",
"implementation": "EXTUB(long m, long n) /* EXTU.B Rm,Rn */\r\n{\r\n R[n] = R[m];\r\n R[n] &= 0x000000FF;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1101",
"desc": "Rm,Rn",
"family": "EXTU.W",
"name": "EXTUW",
"operands": "(long m, long n)",
"implementation": "EXTUW(long m, long n) /* EXTU.W Rm,Rn */\r\n{\r\n R[n] = R[m];\r\n R[n] &= 0x0000FFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn11100011",
"desc": "@Rn",
"family": "ICBI",
"name": "ICBI",
"operands": "(int n)",
"implementation": "ICBI(int n) /* ICBI @Rn */\r\n{\r\n invalidate_instruction_cache_block(R[n]);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00101011",
"desc": "@Rn",
"family": "JMP",
"name": "JMP",
"operands": "(int n)",
"implementation": "JMP(int n)/* JMP @Rn */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n PC = R[n];\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0100mmmm00011110",
"desc": "Rm,GBR",
"family": "LDC",
"name": "LDCGBR",
"operands": "(int m)",
"implementation": "LDCGBR(int m) /* LDC Rm,GBR */\r\n {\r\n GBR = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00101110",
"desc": "Rm,VBR",
"family": "LDC",
"name": "LDCVBR",
"operands": "(int m)",
"implementation": "LDCVBR(int m) /* LDC Rm,VBR : Privileged */\r\n {\r\n VBR = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00111010",
"desc": "Rm,SGR",
"family": "LDC",
"name": "LDCSGR",
"operands": "(int m)",
"implementation": "LDCSGR(int m) /* LDC Rm,SGR : Privileged */\r\n {\r\n SGR = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00111110",
"desc": "Rm,SSR",
"family": "LDC",
"name": "LDCSSR",
"operands": "(int m)",
"implementation": "LDCSSR(int m) /* LDC Rm,SSR : Privileged */\r\n {\r\n SSR = R[m],\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm01001110",
"desc": "Rm,SPC",
"family": "LDC",
"name": "LDCSPC",
"operands": "(int m)",
"implementation": "LDCSPC(int m) /* LDC Rm,SPC : Privileged */\r\n {\r\n SPC = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11111010",
"desc": "Rm,DBR",
"family": "LDC",
"name": "LDCDBR",
"operands": "(int m)",
"implementation": "LDCDBR(int m) /* LDC Rm,DBR : Privileged */\r\n {\r\n DBR = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10001110",
"desc": "Rm,R0_BANK",
"family": "LDC",
"name": "LDCR0_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10011110",
"desc": "Rm,R1_BANK",
"family": "LDC",
"name": "LDCR1_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10101110",
"desc": "Rm,R2_BANK",
"family": "LDC",
"name": "LDCR2_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10111110",
"desc": "Rm,R3_BANK",
"family": "LDC",
"name": "LDCR3_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11001110",
"desc": "Rm,R4_BANK",
"family": "LDC",
"name": "LDCR4_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11011110",
"desc": "Rm,R5_BANK",
"family": "LDC",
"name": "LDCR5_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11101110",
"desc": "Rm,R6_BANK",
"family": "LDC",
"name": "LDCR6_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11111110",
"desc": "Rm,R7_BANK",
"family": "LDC",
"name": "LDCR7_BANK",
"operands": "(int m)",
"implementation": "LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = R[m];\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00010111",
"desc": "@Rm+,GBR",
"family": "LDC.L",
"name": "LDCMGBR",
"operands": "(int m)",
"implementation": "LDCMGBR(int m) /* LDC.L @Rm+,GBR */\r\n {\r\n GBR=Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00100111",
"desc": "@Rm+,VBR",
"family": "LDC.L",
"name": "LDCMVBR",
"operands": "(int m)",
"implementation": "LDCMVBR(int m) /* LDC.L @Rm+,VBR : Privileged */\r\n {\r\n VBR = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00110110",
"desc": "@Rm+,SGR",
"family": "LDC.L",
"name": "LDCMSGR",
"operands": "(int m)",
"implementation": "LDCMSGR(int m) /* LDC.L @Rm+,SGR : Privileged */\r\n {\r\n SGR = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00110111",
"desc": "@Rm+,SSR",
"family": "LDC.L",
"name": "LDCMSSR",
"operands": "(int m)",
"implementation": "LDCMSSR(int m) /* LDC.L @Rm+,SSR : Privileged */\r\n {\r\n SSR=Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm01000111",
"desc": "@Rm+,SPC",
"family": "LDC.L",
"name": "LDCMSPC",
"operands": "(int m)",
"implementation": "LDCMSPC(int m) /* LDC.L @Rm+,SPC : Privileged */\r\n {\r\n SPC = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11110110",
"desc": "@Rm+,DBR",
"family": "LDC.L",
"name": "LDCMDBR",
"operands": "(int m)",
"implementation": "LDCMDBR(int m) /* LDC.L @Rm+,DBR : Privileged */\r\n {\r\n DBR = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10000111",
"desc": "@Rm+,R0_BANK",
"family": "LDC.L",
"name": "LDCMR0_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10010111",
"desc": "@Rm+,R1_BANK",
"family": "LDC.L",
"name": "LDCMR1_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10100111",
"desc": "@Rm+,R2_BANK",
"family": "LDC.L",
"name": "LDCMR2_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm10110111",
"desc": "@Rm+,R3_BANK",
"family": "LDC.L",
"name": "LDCMR3_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11000111",
"desc": "@Rm+,R4_BANK",
"family": "LDC.L",
"name": "LDCMR4_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11010111",
"desc": "@Rm+,R5_BANK",
"family": "LDC.L",
"name": "LDCMR5_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11100111",
"desc": "@Rm+,R6_BANK",
"family": "LDC.L",
"name": "LDCMR6_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm11110111",
"desc": "@Rm+,R7_BANK",
"family": "LDC.L",
"name": "LDCMR7_BANK",
"operands": "(Long m)",
"implementation": "LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */\r\n /* n=0-7 */\r\n {\r\n Rn_BANK = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n }"
},
{
"code": "0100mmmm00001010",
"desc": "Rm,MACH",
"family": "LDS",
"name": "LDSMACH",
"operands": "(long m)",
"implementation": "LDSMACH(long m) /* LDS Rm,MACH */\r\n{\r\n MACH = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00011010",
"desc": "Rm,MACL",
"family": "LDS",
"name": "LDSMACL",
"operands": "(long m)",
"implementation": "LDSMACL(long m) /* LDS Rm,MACL */\r\n{\r\n MACL = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00101010",
"desc": "Rm,PR",
"family": "LDS",
"name": "LDSPR",
"operands": "(long m)",
"implementation": "LDSPR(long m) /* LDS Rm,PR */\r\n{\r\n PR = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00000110",
"desc": "@Rm+,MACH",
"family": "LDS.L",
"name": "LDSMMACH",
"operands": "(long m)",
"implementation": "LDSMMACH(long m) /* LDS.L @Rm+,MACH */\r\n{\r\n MACH = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00010110",
"desc": "@Rm+,MACL",
"family": "LDS.L",
"name": "LDSMMACL",
"operands": "(long m)",
"implementation": "LDSMMACL(long m) /* LDS.L @Rm+,MACL */\r\n{\r\n MACL = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00100110",
"desc": "@Rm+,PR",
"family": "LDS.L",
"name": "LDSMPR",
"operands": "(long m)",
"implementation": "LDSMPR(long m) /* LDS.L @Rm+,PR */\r\n{\r\n PR = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000111000",
"desc": "PTEH/PTEL",
"family": "LDTLB",
"name": "LDTLB",
"operands": "( )",
"implementation": "LDTLB( ) /*LDTLB */\r\n{\r\n TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;\r\n TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;\r\n TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;\r\n TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 |\r\n (PTEL & 0x00000010) >> 4;\r\n TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;\r\n TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;\r\n TLB[MMUCR.URC].WT = (PTEH & 0x00000001);\r\n TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;\r\n TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;\r\n TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm1111",
"desc": "@Rm+,@Rn+",
"family": "MAC.L",
"name": "MACL_",
"operands": "(long m, long n)",
"implementation": "MACL(long m, long n) /* MAC.L @Rm+,@Rn+ */\r\n{\r\n unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;\r\n unsigned long temp0,temp1,temp2,temp3;\r\n long tempm,tempn,fnLmL;\r\n tempn = (long)Read_Long(R[n]);\r\n R[n] += 4;\r\n tempm = (long)Read_Long(R[m]);\r\n R[m] += 4;\r\n if ((long)(tempn^tempm)<0) fnLmL = -1;\r\n else fnLmL = 0;\r\n if (tempn<0) tempn = 0-tempn;\r\n if (tempm<0) tempm = 0-tempm;\r\n temp1 = (unsigned long)tempn;\r\n temp2 = (unsigned long)tempm;\r\n RnL = temp1&0x0000FFFF;\r\n RnH = (temp1>>16) & 0x0000FFFF;\r\n RmL = temp2 & 0x0000FFFF;\r\n RmH = (temp2>>16) & 0x0000FFFF;\r\n temp0 = RmL*RnL;\r\n temp1 = RmH*RnL;\r\n temp2 = RmL*RnH;\r\n temp3 = RmH*RnH;\r\n Res2 = 0;\r\nRes1 = temp1 + temp2;\r\nif (Res1<temp1) Res2 += 0x00010000;\r\ntemp1 =(Res1<<16) & 0xFFFF0000;\r\nRes0 = temp0 + temp1;\r\nif (Res0<temp0) Res2++;\r\nRes2 = Res2 + ((Res1>>16) & 0x0000FFFF) + temp3;\r\nif(fnLmL<0){\r\n Res2 = ~\r\nRes2;\r\n if (Res0==0) Res2++;\r\n else Res0 = (~\r\nRes0)+1;\r\n}\r\nif(S==1){\r\n Res0 = MACL + Res0;\r\n if (MACL>Res0) Res2++;\r\n if (MACH & 0x00008000);\r\n else Res2 += MACH|0xFFFF0000;\r\n Res2 += MACH&0x00007FFF;\r\n if(((long)Res2<0)&&(Res2 < 0xFFFF8000)){\r\n Res2 = 0xFFFF8000;\r\n Res0 = 0x00000000;\r\n }\r\n if(((long)Res2>0)&&(Res2 > 0x00007FFF)){\r\n Res2 = 0x00007FFF;\r\n Res0 = 0xFFFFFFFF;\r\n };\r\n MACH = (Res2 & 0x0000FFFF)|(MACH & 0xFFFF0000);\r\n MACL = Res0;\r\n}\r\n else {\r\n Res0 = MACL + Res0;\r\n if (MACL>Res0) Res2++;\r\n Res2 += MACH;\r\n MACH = Res2;\r\n MACL = Res0;\r\n }\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnnmmmm1111",
"desc": "@Rm+,@Rn+",
"family": "MAC.W",
"name": "MACW",
"operands": "(long m, long n)",
"implementation": "MACW(long m, long n) /* MAC.W @Rm+,@Rn+ */\r\n{\r\n long tempm,tempn,dest,src,ans;\r\n unsigned long templ;\r\n tempn = (long)Read_Word(R[n]);\r\n R[n] += 2;\r\n tempm = (long)Read_Word(R[m]);\r\n R[m] += 2;\r\n templ = MACL;\r\n tempm = ((long)(short)tempn*(long)(short)tempm);\r\n if ((long)MACL>=0) dest = 0;\r\n else dest = 1;\r\n if ((long)tempm>=0) {\r\n src = 0;\r\n tempn = 0;\r\n }\r\n else {\r\n src = 1;\r\n tempn = 0xFFFFFFFF;\r\n }\r\n src += dest;\r\n MACL += tempm;\r\n if ((long)MACL>=0) ans = 0;\r\n else ans = 1;\r\n ans += dest;\r\n if (S==1) {\r\n if (ans==1) {\r\n if (src==0) MACL = 0x7FFFFFFF;\r\n if (src==2) MACL = 0x80000000;\r\n }\r\n }\r\n else {\r\n MACH += tempn;\r\n if (templ>MACL) MACH += 1;\r\n }\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0011",
"desc": "Rm,Rn",
"family": "MOV",
"name": "MOV",
"operands": "(long m, long n)",
"implementation": "MOV(long m, long n) /* MOV Rm,Rn */\r\n{\r\n R[n] = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0000",
"desc": "Rm,@Rn",
"family": "MOV.B",
"name": "MOVBS",
"operands": "(long m, long n)",
"implementation": "MOVBS(long m, long n) /* MOV.B Rm,@Rn */\r\n{\r\n Write_Byte(R[n],R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0001",
"desc": "Rm,@Rn",
"family": "MOV.W",
"name": "MOVWS",
"operands": "(long m, long n)",
"implementation": "MOVWS(long m, long n) /* MOV.W Rm,@Rn */\r\n{\r\n Write_Word(R[n],R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0010",
"desc": "Rm,@Rn",
"family": "MOV.L",
"name": "MOVLS",
"operands": "(long m, long n)",
"implementation": "MOVLS(long m, long n) /* MOV.L Rm,@Rn */\r\n{\r\n Write_Long(R[n],R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0000",
"desc": "@Rm,Rn",
"family": "MOV.B",
"name": "MOVBL",
"operands": "(long m, long n)",
"implementation": "MOVBL(long m, long n) /* MOV.B @Rm,Rn */\r\n{\r\n R[n] = (long)Read_Byte(R[m]);\r\n if ((R[n]&0x80)==0) R[n] &= 0x000000FF;\r\n else R[n] |= 0xFFFFFF00;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0001",
"desc": "@Rm,Rn",
"family": "MOV.W",
"name": "MOVWL",
"operands": "(long m, long n)",
"implementation": "MOVWL(long m, long n) /* MOV.W @Rm,Rn */\r\n{\r\n R[n] = (long)Read_Word(R[m]);\r\n if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;\r\n else R[n] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0010",
"desc": "@Rm,Rn",
"family": "MOV.L",
"name": "MOVLL",
"operands": "(long m, long n)",
"implementation": "MOVLL(long m, long n) /* MOV.L @Rm,Rn */\r\n{\r\n R[n] = Read_Long(R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0100",
"desc": "Rm,@-Rn",
"family": "MOV.B",
"name": "MOVBM",
"operands": "(long m, long n)",
"implementation": "MOVBM(long m, long n) /* MOV.B Rm,@-Rn */\r\n{\r\n Write_Byte(R[n]-1,R[m]);\r\n R[n] -= 1;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0101",
"desc": "Rm,@-Rn",
"family": "MOV.W",
"name": "MOVWM",
"operands": "(long m, long n)",
"implementation": "MOVWM(long m, long n) /* MOV.W Rm,@-Rn */\r\n{\r\n Write_Word(R[n]-2,R[m]);\r\n R[n] -= 2;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm0110",
"desc": "Rm,@-Rn",
"family": "MOV.L",
"name": "MOVLM",
"operands": "(long m, long n)",
"implementation": "MOVLM(long m, long n) /* MOV.L Rm,@-Rn */\r\n{\r\n Write_Long(R[n]-4,R[m]);\r\n R[n] -= 4;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0100",
"desc": "@Rm+,Rn",
"family": "MOV.B",
"name": "MOVBP",
"operands": "(long m, long n)",
"implementation": "MOVBP(long m, long n) /* MOV.B @Rm+,Rn */\r\n{\r\n R[n] = (long)Read_Byte(R[m]);\r\n if ((R[n]&0x80)==0) R[n] &= 0x000000FF;\r\n else R[n] |= 0xFFFFFF00;\r\n if (n!=m) R[m] += 1;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0101",
"desc": "@Rm+,Rn",
"family": "MOV.W",
"name": "MOVWP",
"operands": "(long m, long n)",
"implementation": "MOVWP(long m, long n) /* MOV.W @Rm+,Rn */\r\n{\r\n R[n] = (long)Read_Word(R[m]);\r\n if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;\r\n else R[n] |= 0xFFFF0000;\r\n if (n!=m) R[m] += 2;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0110",
"desc": "@Rm+,Rn",
"family": "MOV.L",
"name": "MOVLP",
"operands": "(long m, long n)",
"implementation": "MOVLP(long m, long n) /* MOV.L @Rm+,Rn */\r\n{\r\n R[n] = Read_Long(R[m]);\r\n if (n!=m) R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm0100",
"desc": "Rm,@(R0,Rn)",
"family": "MOV.B",
"name": "MOVBS0",
"operands": "(long m, long n)",
"implementation": "MOVBS0(long m, long n) /* MOV.B Rm,@(R0,Rn) */\r\n{\r\n Write_Byte(R[n]+R[0],R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm0101",
"desc": "Rm,@(R0,Rn)",
"family": "MOV.W",
"name": "MOVWS0",
"operands": "(long m, long n)",
"implementation": "MOVWS0(long m, long n) /* MOV.W Rm,@(R0,Rn) */\r\n{\r\n Write_Word(R[n]+R[0],R[m]);\r\n PC+=2;\r\n}"
},
{
"code": "0000nnnnmmmm0110",
"desc": "Rm,@(R0,Rn)",
"family": "MOV.L",
"name": "MOVLS0",
"operands": "(long m, long n)",
"implementation": "MOVLS0(long m, long n) /* MOV.L Rm,@(R0,Rn) */\r\n{\r\n Write_Long(R[n]+R[0],R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm1100",
"desc": "@(R0,Rm),Rn",
"family": "MOV.B",
"name": "MOVBL0",
"operands": "(long m, long n)",
"implementation": "MOVBL0(long m, long n) /* MOV.B @(R0,Rm),Rn */\r\n{\r\n R[n] = (long)Read_Byte(R[m]+R[0]);\r\n if ((R[n]&0x80)==0) R[n] &= 0x000000FF;\r\n else R[n] |= 0xFFFFFF00;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm1101",
"desc": "@(R0,Rm),Rn",
"family": "MOV.W",
"name": "MOVWL0",
"operands": "(long m, long n)",
"implementation": "MOVWL0(long m, long n) /* MOV.W @(R0,Rm),Rn */\r\n{\r\n R[n] = (long)Read_Word(R[m]+R[0]);\r\n if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;\r\n else R[n] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm1110",
"desc": "@(R0,Rm),Rn",
"family": "MOV.L",
"name": "MOVLL0",
"operands": "(long m, long n)",
"implementation": "MOVLL0(long m, long n) /* MOV.L @(R0,Rm),Rn */\r\n{\r\n R[n] = Read_Long(R[m]+R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "1110nnnniiiiiiii",
"desc": "#imm,Rn",
"family": "MOV",
"name": "MOVI",
"operands": "(int i, int n)",
"implementation": "MOVI(int i, int n) /* MOV #imm,Rn */\r\n{\r\n if ((i&0x80)==0) R[n] = (0x000000FF & i);\r\n else R[n] = (0xFFFFFF00 | i);\r\n PC += 2;\r\n}"
},
{
"code": "1001nnnndddddddd",
"desc": "@(disp*,PC),Rn",
"family": "MOV.W",
"name": "MOVWI",
"operands": "(int d, int n)",
"implementation": "MOVWI(int d, int n) /* MOV.W @(disp,PC),Rn */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n R[n] = (int)Read_Word(PC+4+(disp<<1));\r\n if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;\r\n else R[n] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "1101nnnndddddddd",
"desc": "@(disp*,PC),Rn",
"family": "MOV.L",
"name": "MOVLI",
"operands": "(int d, int n)",
"implementation": "MOVLI(int d, int n)/* MOV.L @(disp,PC),Rn */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & (int)d);\r\n R[n] = Read_Long((PC & 0xFFFFFFFC)+4+(disp<<2));\r\n PC += 2;\r\n}"
},
{
"code": "11000100dddddddd",
"desc": "@(disp*,GBR),R0",
"family": "MOV.B",
"name": "MOVBLG",
"operands": "(int d)",
"implementation": "MOVBLG(int d) /* MOV.B @(disp,GBR),R0 */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n R[0] = (int)Read_Byte(GBR+disp);\r\n if ((R[0]&0x80)==0) R[0] &= 0x000000FF;\r\n else R[0] |= 0xFFFFFF00;\r\n PC += 2;\r\n}"
},
{
"code": "11000101dddddddd",
"desc": "@(disp*,GBR),R0",
"family": "MOV.W",
"name": "MOVWLG",
"operands": "(int d)",
"implementation": "MOVWLG(int d) /* MOV.W @(disp,GBR),R0 */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n R[0] = (int)Read_Word(GBR+(disp<<1));\r\n if ((R[0]&0x8000)==0) R[0] &= 0x0000FFFF;\r\n else R[0] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "11000110dddddddd",
"desc": "@(disp*,GBR),R0",
"family": "MOV.L",
"name": "MOVLLG",
"operands": "(int d)",
"implementation": "MOVLLG(int d) /* MOV.L @(disp,GBR),R0 */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n R[0] = Read_Long(GBR+(disp<<2));\r\n PC += 2;\r\n}"
},
{
"code": "11000000dddddddd",
"desc": "R0,@(disp*,GBR)",
"family": "MOV.B",
"name": "MOVBSG",
"operands": "(int d)",
"implementation": "MOVBSG(int d) /* MOV.B R0,@(disp,GBR) */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n Write_Byte(GBR+disp,R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "11000001dddddddd",
"desc": "R0,@(disp*,GBR)",
"family": "MOV.W",
"name": "MOVWSG",
"operands": "(int d)",
"implementation": "MOVWSG(int d) /* MOV.W R0,@(disp,GBR) */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n Write_Word(GBR+(disp<<1),R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "11000010dddddddd",
"desc": "R0,@(disp*,GBR)",
"family": "MOV.L",
"name": "MOVLSG",
"operands": "(int d)",
"implementation": "MOVLSG(int d) /* MOV.L R0,@(disp,GBR) */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & (long)d);\r\n Write_Long(GBR+(disp<<2),R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "10000000nnnndddd",
"desc": "R0,@(disp*,Rn)",
"family": "MOV.B",
"name": "MOVBS4",
"operands": "(long d, long n)",
"implementation": "MOVBS4(long d, long n) /* MOV.B R0,@(disp,Rn) */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n Write_Byte(R[n]+disp,R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "10000001nnnndddd",
"desc": "R0,@(disp*,Rn)",
"family": "MOV.W",
"name": "MOVWS4",
"operands": "(long d, long n)",
"implementation": "MOVWS4(long d, long n) /* MOV.W R0,@(disp,Rn) */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n Write_Word(R[n]+(disp<<1),R[0]);\r\n PC += 2;\r\n}"
},
{
"code": "0001nnnnmmmmdddd",
"desc": "Rm,@(disp*,Rn)",
"family": "MOV.L",
"name": "MOVLS4",
"operands": "(long m, long d, long n)",
"implementation": "MOVLS4(long m, long d, long n) /* MOV.L Rm,@(disp,Rn) */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n Write_Long(R[n]+(disp<<2),R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "10000100mmmmdddd",
"desc": "@(disp*,Rm),R0",
"family": "MOV.B",
"name": "MOVBL4",
"operands": "(long m, long d)",
"implementation": "MOVBL4(long m, long d) /* MOV.B @(disp,Rm),R0 */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n R[0] = Read_Byte(R[m]+disp);\r\n if ((R[0]&0x80)==0) R[0] &= 0x000000FF;\r\n else R[0] |= 0xFFFFFF00;\r\n PC += 2;\r\n}"
},
{
"code": "10000101mmmmdddd",
"desc": "@(disp*,Rm),R0",
"family": "MOV.W",
"name": "MOVWL4",
"operands": "(long m, long d)",
"implementation": "MOVWL4(long m, long d) /* MOV.W @(disp,Rm),R0 */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n R[0] = Read_Word(R[m]+(disp<<1));\r\n if ((R[0]&0x8000)==0) R[0] &= 0x0000FFFF;\r\n else R[0] |= 0xFFFF0000;\r\n PC += 2;\r\n}"
},
{
"code": "0101nnnnmmmmdddd",
"desc": "@(disp*,Rm),Rn",
"family": "MOV.L",
"name": "MOVLL4",
"operands": "(long m, long d, long n)",
"implementation": "MOVLL4(long m, long d, long n) /* MOV.L @(disp,Rm),Rn */\r\n{\r\n long disp;\r\n disp = (0x0000000F & (long)d);\r\n R[n] = Read_Long(R[m]+(disp<<2));\r\n PC += 2;\r\n}"
},
{
"code": "11000111dddddddd",
"desc": "@(disp*,PC),R0",
"family": "MOVA",
"name": "MOVA",
"operands": "(int d)",
"implementation": "MOVA(int d) /* MOVA @(disp,PC),R0 */\r\n{\r\n unsigned int disp;\r\n disp = (unsigned int)(0x000000FF & d);\r\n R[0] = (PC&0xFFFFFFFC) + 4 + (disp<<2);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn11000011",
"desc": "R0,@Rn",
"family": "MOVCA.L",
"name": "MOVCAL",
"operands": "(int n)",
"implementation": "MOVCAL(int n) /*MOVCA.L R0,@Rn */\r\n {\r\n if ((is_write_back_memory(R[n]))\r\n && (look_up_in_operand_cache(R[n]) == MISS))\r\n allocate_operand_cache_block(R[n]);\r\n Write_Long(R[n], R[0]);\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn01110011",
"desc": "R0,@Rn",
"family": "MOVCO.L",
"name": "MOVCO",
"operands": "(long n)",
"implementation": "MOVCO(long n) /* MOVCO Rn,@Rn */\r\n{\r\n T = LDST;\r\n if(T==1)\r\n Write_Long(R[n],R[0]);\r\n LDST = 0;\r\n PC += 2\r\n}"
},
{
"code": "0000nnnn01100011",
"desc": "@Rm,R0",
"family": "MOVLI.L",
"name": "MOVLINK",
"operands": "(long m)",
"implementation": "MOVLINK(long m) /* MOVLI Rm,@Rn */\r\n{\r\n LDST = 1;\r\n R[0] = Read_Long(R[m]);\r\n PC += 2\r\n}"
},
{
"code": "0000nnnn00101001",
"desc": "Rn",
"family": "MOVT",
"name": "MOVT",
"operands": "(long n)",
"implementation": "MOVT(long n) /* MOVT Rn */\r\n{\r\n R[n] = (0x00000001 & SR);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10101001",
"desc": "@Rm,R0",
"family": "MOVUA.L",
"name": "MOVUAL",
"operands": "(int n)",
"implementation": "MOVUAL(int n) /* MOVUA.L Rm,R0*/\r\n{\r\n Read_Unaligned_Long(R0,R[n]);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn11101001",
"desc": "@Rm+,R0",
"family": "MOVUA.L",
"name": "MOVUALP",
"operands": "(int n)",
"implementation": "MOVUALP(int n) /* MOVUA.L Rm+,R0*/\r\n{\r\n Read_Unaligned_Long(R0,R[n]);\r\n if(n != 0) R[n] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnnmmmm0111",
"desc": "Rm,Rn",
"family": "MUL.L",
"name": "MULL",
"operands": "(long m, long n)",
"implementation": "MULL(long m, long n) /* MUL.L Rm,Rn */\r\n{\r\n MACL = R[n]*R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1111",
"desc": "Rm,Rn",
"family": "MULS.W",
"name": "MULS",
"operands": "(long m, long n)",
"implementation": "MULS(long m, long n) /* MULS Rm,Rn */\r\n{\r\n MACL = ((long)(short)R[n]*(long)(short)R[m]);\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1110",
"desc": "Rm,Rn",
"family": "MULU.W",
"name": "MULU",
"operands": "(long m, long n)",
"implementation": "MULU(long m, long n) /* MULU Rm,Rn */\r\n{\r\n MACL = (unsigned long)(unsigned short)R[n]*\r\n (unsigned long)(unsigned short)R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1011",
"desc": "Rm,Rn",
"family": "NEG",
"name": "NEG",
"operands": "(long m, long n)",
"implementation": "NEG(long m, long n) /* NEG Rm,Rn */\r\n{\r\n R[n] = 0-R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1010",
"desc": "Rm,Rn",
"family": "NEGC",
"name": "NEGC",
"operands": "(long m, long n)",
"implementation": "NEGC(long m, long n) /* NEGC Rm,Rn */\r\n{\r\n unsigned long temp;\r\n temp = 0-R[m];\r\n R[n] = temp-T;\r\n if (0<temp) T = 1;\r\n else T = 0;\r\n if (temp<R[n]) T = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000001001",
"desc": "No",
"family": "NOP",
"name": "NOP",
"operands": "( )",
"implementation": "NOP( ) /* NOP */\r\n{\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm0111",
"desc": "Rm,Rn",
"family": "NOT",
"name": "NOT",
"operands": "(long m, long n)",
"implementation": "NOT(long m, long n) /* NOT Rm,Rn */\r\n{\r\n R[n] = ~R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10010011",
"desc": "@Rn",
"family": "OCBI",
"name": "OCBI",
"operands": "(int n)",
"implementation": "OCBI(int n) /* OCBI @Rn */\r\n{\r\n invalidate_operand_cache_block(R[n]);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10100011",
"desc": "@Rn",
"family": "OCBP",
"name": "OCBP",
"operands": "(int n)",
"implementation": "OCBP(int n) /* OCBP @Rn */\r\n{\r\n if(is_dirty_block(R[n])) write_back(R[n])\r\n invalidate_operand_cache_block(R[n]);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10110011",
"desc": "@Rn",
"family": "OCBWB",
"name": "OCBWB",
"operands": "(int n)",
"implementation": "OCBWB(int n) /* OCBWB @Rn */\r\n {\r\n if(is_dirty_block(R[n])) write_back(R[n]);\r\n PC += 2;\r\n }"
},
{
"code": "0010nnnnmmmm1011",
"desc": "Rm,Rn",
"family": "OR",
"name": "OR",
"operands": "(long m, long n)",
"implementation": "OR(long m, long n) /* OR Rm,Rn */\r\n{\r\n R[n] |= R[m];\r\n PC += 2;\r\n}"
},
{
"code": "11001011iiiiiiii",
"desc": "#imm,R0",
"family": "OR",
"name": "ORI",
"operands": "(long i)",
"implementation": "ORI(long i) /* OR #imm,R0 */\r\n{\r\n R[0] |= (0x000000FF & (long)i);\r\n PC += 2;\r\n}"
},
{
"code": "11001111iiiiiiii",
"desc": "#imm,@(R0,GBR)",
"family": "OR.B",
"name": "ORM",
"operands": "(long i)",
"implementation": "ORM(long i) /* OR.B #imm,@(R0,GBR) */\r\n{\r\n long temp;\r\n temp = (long)Read_Byte(GBR+R[0]);\r\n temp |= (0x000000FF & (long)i);\r\n Write_Byte(GBR+R[0],temp);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10000011",
"desc": "@Rn",
"family": "PREF",
"name": "PREF",
"operands": "(int n)",
"implementation": "PREF(int n) /* PREF @Rn */\r\n{\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn11010011",
"desc": "@Rn",
"family": "PREFI",
"name": "PREFI",
"operands": "(int n)",
"implementation": "PREFI(int n) /* PREFI @Rn*/\r\n{\r\n prefetch_instruction_cache_block(R[n]);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00100100",
"desc": "Rn",
"family": "ROTCL",
"name": "ROTCL",
"operands": "(long n)",
"implementation": "ROTCL(long n) /* ROTCL Rn */\r\n{\r\n long temp;\r\n if ((R[n] & 0x80000000)==0) temp=0;\r\n else temp = 1;\r\n R[n] <<= 1;\r\n if (T==1) R[n] |= 0x00000001;\r\n else R[n] &= 0xFFFFFFFE;\r\n if (temp==1) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00100101",
"desc": "Rn",
"family": "ROTCR",
"name": "ROTCR",
"operands": "(long n)",
"implementation": "ROTCR(long n) /* ROTCR Rn */\r\n{\r\n long temp;\r\n if ((R[n] & 0x00000001)==0) temp = 0;\r\n else temp = 1;\r\n R[n] >>= 1;\r\n if (T==1) R[n] |= 0x80000000;\r\n else R[n] &= 0x7FFFFFFF;\r\n if (temp==1) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000100",
"desc": "Rn",
"family": "ROTL",
"name": "ROTL",
"operands": "(long n)",
"implementation": "ROTL(long n) /* ROTL Rn */\r\n{\r\n if ((R[n]&0x80000000)==0) T = 0;\r\n else T = 1;\r\n R[n] <<= 1;\r\n if (T==1) R[n] |= 0x00000001;\r\n else R[n] &= 0xFFFFFFFE;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000101",
"desc": "Rn",
"family": "ROTR",
"name": "ROTR",
"operands": "(long n)",
"implementation": "ROTR(long n) /* ROTR Rn */\r\n{\r\n if ((R[n] & 0x00000001)==0) T = 0;\r\n else T = 1;\r\n R[n] >>= 1;\r\n if (T==1) R[n] |= 0x80000000;\r\n else R[n] &= 0x7FFFFFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000101011",
"desc": "SSR",
"family": "RTE",
"name": "RTE",
"operands": "( )",
"implementation": "RTE( ) /* RTE */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n SR = SSR;\r\n PC = SPC;\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0000000000001011",
"desc": "PR",
"family": "RTS",
"name": "RTS",
"operands": "( )",
"implementation": "RTS( ) /* RTS */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n PC = PR;\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0000000001011000",
"desc": "1",
"family": "SETS",
"name": "SETS",
"operands": "( )",
"implementation": "SETS( ) /* SETS */\r\n{\r\n S = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000011000",
"desc": "1",
"family": "SETT",
"name": "SETT",
"operands": "( )",
"implementation": "SETT( ) /* SETT */\r\n{\r\n T = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnnmmmm1100",
"desc": "Rm,Rn",
"family": "SHAD",
"name": "SHAD",
"operands": "(int m, int n)",
"implementation": "SHAD(int m, int n) /*SHAD Rm,Rn */\r\n{\r\n int sgn = R[m] & 0x80000000;\r\n if (sgn==0)\r\n R[n] <<= (R[m] & 0x1F);\r\n else if ((R[m] & 0x1F) == 0) {\r\n if ((R[n] & 0x80000000) == 0)\r\n R[n] = 0;\r\n else\r\n R[n] = 0xFFFFFFFF;\r\n }\r\n else\r\n R[n] = (long)R[n] >> ((~R[m] & 0x1F)+1);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00100000",
"desc": "Rn",
"family": "SHAL",
"name": "SHAL",
"operands": "(long n)",
"implementation": "SHAL(long n) /* SHAL Rn (Same as SHLL) */\r\n{\r\n if ((R[n]&0x80000000)==0) T = 0;\r\n else T = 1;\r\n R[n] <<= 1;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00100001",
"desc": "Rn",
"family": "SHAR",
"name": "SHAR",
"operands": "(long n)",
"implementation": "SHAR(long n) /* SHAR Rn */\r\n{\r\n long temp;\r\n if ((R[n]&0x00000001)==0) T = 0;\r\n else T = 1;\r\n if ((R[n]&0x80000000)==0) temp = 0;\r\n else temp = 1;\r\n R[n] >>= 1;\r\n if (temp==1) R[n] |= 0x80000000;\r\n else R[n] &= 0x7FFFFFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnnmmmm1101",
"desc": "Rm,Rn",
"family": "SHLD",
"name": "SHLD",
"operands": "(int m, int n)",
"implementation": "SHLD(int m, int n)/*SHLD Rm,Rn */\r\n{\r\n int sgn = R[m] & 0x80000000;\r\n if (sgn == 0)\r\n R[n] <<= (R[m] & 0x1F);\r\n else if ((R[m] & 0x1F) == 0)\r\n R[n] = 0;\r\n else\r\n R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F)+1);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000000",
"desc": "Rn",
"family": "SHLL",
"name": "SHLL",
"operands": "(long n)",
"implementation": "SHLL(long n) /* SHLL Rn (Same as SHAL) */\r\n{\r\n if ((R[n]&0x80000000)==0) T = 0;\r\n else T = 1;\r\n R[n] <<= 1;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00001000",
"desc": "Rn",
"family": "SHLL2",
"name": "SHLL2",
"operands": "(long n)",
"implementation": "SHLL2(long n) /* SHLL2 Rn */\r\n{\r\n R[n] <<= 2;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00011000",
"desc": "Rn",
"family": "SHLL8",
"name": "SHLL8",
"operands": "(long n)",
"implementation": "SHLL8(long n) /* SHLL8 Rn */\r\n{\r\n R[n] <<= 8;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00101000",
"desc": "Rn",
"family": "SHLL16",
"name": "SHLL16",
"operands": "(long n)",
"implementation": "SHLL16(long n) /* SHLL16 Rn */\r\n{\r\n R[n] <<= 16;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000001",
"desc": "Rn",
"family": "SHLR",
"name": "SHLR",
"operands": "(long n)",
"implementation": "SHLR(long n) /* SHLR Rn */\r\n{\r\n if ((R[n] & 0x00000001)==0) T = 0;\r\n else T = 1;\r\n R[n] >>= 1;\r\n R[n] &= 0x7FFFFFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00001001",
"desc": "Rn",
"family": "SHLR2",
"name": "SHLR2",
"operands": "(long n)",
"implementation": "SHLR2(long n) /* SHLR2 Rn */\r\n{\r\n R[n] >>= 2;\r\n R[n] &= 0x3FFFFFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00011001",
"desc": "Rn",
"family": "SHLR8",
"name": "SHLR8",
"operands": "(long n)",
"implementation": "SHLR8(long n) /* SHLR8 Rn */\r\n{\r\n R[n] >>= 8;\r\n R[n] &= 0x00FFFFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00101001",
"desc": "Rn",
"family": "SHLR16",
"name": "SHLR16",
"operands": "(long n)",
"implementation": "SHLR16(long n) /* SHLR16 Rn */\r\n{\r\n R[n] >>= 16;\r\n R[n] &= 0x0000FFFF;\r\n PC += 2;\r\n}"
},
{
"code": "0000000000011011",
"desc": "Sleep",
"family": "SLEEP",
"name": "SLEEP",
"operands": "( )",
"implementation": "SLEEP( ) /* SLEEP */\r\n{\r\n Sleep_standby();\r\n}"
},
{
"code": "0000nnnn00010010",
"desc": "GBR,Rn",
"family": "STC",
"name": "STCGBR",
"operands": "(int n)",
"implementation": "STCGBR(int n) /* STC GBR,Rn */\r\n {\r\n R[n] = GBR;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn00100010",
"desc": "VBR,Rn",
"family": "STC",
"name": "STCVBR",
"operands": "(int n)",
"implementation": "STCVBR(int n) /* STC VBR,Rn : Privileged */\r\n {\r\n R[n] = VBR;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn00110010",
"desc": "SSR,Rn",
"family": "STC",
"name": "STCSSR",
"operands": "(int n)",
"implementation": "STCSSR(int n) /* STC SSR,Rn : Privileged */\r\n {\r\n R[n] = SSR;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn01000010",
"desc": "SPC,Rn",
"family": "STC",
"name": "STCSPC",
"operands": "(int n)",
"implementation": "STCSPC(int n) /* STC SPC,Rn : Privileged */\r\n {\r\n R[n] = SPC;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn00111010",
"desc": "SGR,Rn",
"family": "STC",
"name": "STCSGR",
"operands": "(int n)",
"implementation": "STCSGR(int n) /* STC SGR,Rn : Privileged */\r\n {\r\n R[n] = SGR;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn11111010",
"desc": "DBR,Rn",
"family": "STC",
"name": "STCDBR",
"operands": "(int n)",
"implementation": "STCDBR(int n) /* STC DBR,Rn : Privileged */\r\n {\r\n R[n] = DBR;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn10000010",
"desc": "R0_BANK,Rn",
"family": "STC",
"name": "STCR0_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn10010010",
"desc": "R1_BANK,Rn",
"family": "STC",
"name": "STCR1_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn10100010",
"desc": "R2_BANK,Rn",
"family": "STC",
"name": "STCR2_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn10110010",
"desc": "R3_BANK,Rn",
"family": "STC",
"name": "STCR3_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn11000010",
"desc": "R4_BANK,Rn",
"family": "STC",
"name": "STCR4_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn11010010",
"desc": "R5_BANK,Rn",
"family": "STC",
"name": "STCR5_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn11100010",
"desc": "R6_BANK,Rn",
"family": "STC",
"name": "STCR6_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn11110010",
"desc": "R7_BANK,Rn",
"family": "STC",
"name": "STCR7_BANK",
"operands": "(int n)",
"implementation": "STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] = Rm_BANK;\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn00010011",
"desc": "GBR,@-Rn",
"family": "STC.L",
"name": "STCMGBR",
"operands": "(int n)",
"implementation": "STCMGBR(int n) /* STC.L GBR,@-Rn */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],GBR);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn00100011",
"desc": "VBR,@-Rn",
"family": "STC.L",
"name": "STCMVBR",
"operands": "(int n)",
"implementation": "STCMVBR(int n) /* STC.L VBR,@-Rn : Privileged */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],VBR);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn00110011",
"desc": "SSR,@-Rn",
"family": "STC.L",
"name": "STCMSSR",
"operands": "(int n)",
"implementation": "STCMSSR(int n) /* STC.L SSR,@-Rn : Privileged */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],SSR);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn01000011",
"desc": "SPC,@-Rn",
"family": "STC.L",
"name": "STCMSPC",
"operands": "(int n)",
"implementation": "STCMSPC(int n) /* STC.L SPC,@-Rn : Privileged */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],SPC);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn00110010",
"desc": "SGR,@-Rn",
"family": "STC.L",
"name": "STCMSGR",
"operands": "(int n)",
"implementation": "STCMSGR(int n) /* STC.L SGR,@-Rn : Privileged */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],SGR);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn11110010",
"desc": "DBR,@-Rn",
"family": "STC.L",
"name": "STCMDBR",
"operands": "(int n)",
"implementation": "STCMDBR(int n) /* STC.L DBR,@-Rn : Privileged */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],DBR);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn10000011",
"desc": "R0_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR0_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn10010011",
"desc": "R1_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR1_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn10100011",
"desc": "R2_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR2_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn10110011",
"desc": "R3_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR3_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn11000011",
"desc": "R4_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR4_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn11010011",
"desc": "R5_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR5_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn11100011",
"desc": "R6_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR6_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0100nnnn11110011",
"desc": "R7_BANK,@-Rn",
"family": "STC.L",
"name": "STCMR7_BANK",
"operands": "(int n)",
"implementation": "STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */\r\n /* m=0-7 */\r\n {\r\n R[n] -= 4;\r\n Write_Long(R[n],Rm_BANK);\r\n PC += 2;\r\n }"
},
{
"code": "0000nnnn00001010",
"desc": "MACH,Rn",
"family": "STS",
"name": "STSMACH",
"operands": "(int n)",
"implementation": "STSMACH(int n) /* STS MACH,Rn */\r\n{\r\n R[n] = MACH;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn00011010",
"desc": "MACL,Rn",
"family": "STS",
"name": "STSMACL",
"operands": "(int n)",
"implementation": "STSMACL(int n) /* STS MACL,Rn */\r\n{\r\n R[n] = MACL;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn00101010",
"desc": "PR,Rn",
"family": "STS",
"name": "STSPR",
"operands": "(int n)",
"implementation": "STSPR(int n) /* STS PR,Rn */\r\n{\r\n R[n] = PR;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000010",
"desc": "MACH,@-Rn",
"family": "STS.L",
"name": "STSMMACH",
"operands": "(int n)",
"implementation": "STSMMACH(int n) /* STS.L MACH,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],MACH);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00010010",
"desc": "MACL,@-Rn",
"family": "STS.L",
"name": "STSMMACL",
"operands": "(int n)",
"implementation": "STSMMACL(int n) /* STS.L MACL,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],MACL);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00100010",
"desc": "PR,@-Rn",
"family": "STS.L",
"name": "STSMPR",
"operands": "(int n)",
"implementation": "STSMPR(int n) /* STS.L PR,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],PR);\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1000",
"desc": "Rm,Rn",
"family": "SUB",
"name": "SUB",
"operands": "(long m, long n)",
"implementation": "SUB(long m, long n) /* SUB Rm,Rn */\r\n{\r\n R[n] -= R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1010",
"desc": "Rm,Rn",
"family": "SUBC",
"name": "SUBC",
"operands": "(long m, long n)",
"implementation": "SUBC(long m, long n) /* SUBC Rm,Rn */\r\n{\r\n unsigned long tmp0,tmp1;\r\n tmp1 = R[n] - R[m];\r\n tmp0 = R[n];\r\n R[n] = tmp1 - T;\r\n if (tmp0<tmp1) T = 1;\r\n else T = 0;\r\n if (tmp1<R[n]) T = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0011nnnnmmmm1011",
"desc": "Rm,Rn",
"family": "SUBV",
"name": "SUBV",
"operands": "(long m, long n)",
"implementation": "SUBV(long m, long n) /* SUBV Rm,Rn */\r\n{\r\n long dest,src,ans;\r\n if ((long)R[n]>=0) dest = 0;\r\n else dest = 1;\r\n if ((long)R[m]>=0) src = 0;\r\n else src = 1;\r\n src += dest;\r\n R[n] -= R[m];\r\n if ((long)R[n]>=0) ans = 0;\r\n else ans = 1;\r\n ans += dest;\r\n if (src==1) {\r\n if (ans==1) T = 1;\r\n else T = 0;\r\n }\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1000",
"desc": "Rm,Rn",
"family": "SWAP.B",
"name": "SWAPB",
"operands": "(long m, long n)",
"implementation": "SWAPB(long m, long n) /* SWAP.B Rm,Rn */\r\n{\r\n unsigned long temp0,temp1;\r\n temp0 = R[m] & 0xFFFF0000;\r\n temp1 = (R[m] & 0x000000FF) << 8;\r\n R[n] = (R[m] & 0x0000FF00) >> 8;\r\n R[n] = R[n] | temp1 | temp0;\r\n PC += 2;\r\n}"
},
{
"code": "0110nnnnmmmm1001",
"desc": "Rm,Rn",
"family": "SWAP.W",
"name": "SWAPW",
"operands": "(long m, long n)",
"implementation": "SWAPW(long m, long n) /* SWAP.W Rm,Rn */\r\n{\r\n unsigned long temp;\r\n temp = (R[m]>>16)&0x0000FFFF;\r\n R[n] = R[m]<<16;\r\n R[n] |= temp;\r\n PC += 2;\r\n}"
},
{
"code": "0000000010101011",
"desc": "Data",
"family": "SYNCO",
"name": "SYNCO",
"operands": "()",
"implementation": "SYNCO() /* SYNCO*/\r\n{\r\n synchronize_data_operaiton();\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00011011",
"desc": "@Rn",
"family": "TAS.B",
"name": "TAS",
"operands": "(int n)",
"implementation": "TAS(int n) /* TAS.B @Rn */\r\n{\r\n int temp;\r\n temp = (int)Read_Byte(R[n]); /* Bus Lock */\r\n if (temp==0) T = 1;\r\n else T = 0;\r\n temp |= 0x00000080;\r\n Write_Byte(R[n],temp); /* Bus unlock */\r\n PC += 2;\r\n}"
},
{
"code": "11000011iiiiiiii",
"desc": "#imm",
"family": "TRAPA",
"name": "TRAPA",
"operands": "(int i)",
"implementation": "TRAPA(int i) /* TRAPA #imm */\r\n {\r\n int imm;\r\n imm = (0x000000FF & i);\r\n TRA = imm<<2;\r\n SSR = SR;\r\n SPC = PC+2;\r\n SGR = R15;\r\n SR.MD = 1;\r\n SR.BL = 1;\r\n SR.RB=1;\r\n EXPEVT = 0x00000160;\r\n PC = VBR + 0x00000100;\r\n}"
},
{
"code": "0010nnnnmmmm1000",
"desc": "Rm,Rn",
"family": "TST",
"name": "TST",
"operands": "(long m, long n)",
"implementation": "TST(long m, long n) /* TST Rm,Rn */\r\n{\r\n if ((R[n]&R[m])==0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "11001000iiiiiiii",
"desc": "#imm,R0",
"family": "TST",
"name": "TSTI",
"operands": "(long i)",
"implementation": "TSTI(long i) /* TST #imm,R0 */\r\n{\r\n long temp;\r\n temp = R[0]&(0x000000FF & (long)i);\r\n if (temp==0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "11001100iiiiiiii",
"desc": "#imm,@(R0,GBR)",
"family": "TST.B",
"name": "TSTM",
"operands": "(long i)",
"implementation": "TSTM(long i) /* TST.B #imm,@(R0,GBR) */\r\n{\r\n long temp;\r\n temp = (long)Read_Byte(GBR+R[0]);\r\n temp &= (0x000000FF & (long)i);\r\n if (temp==0) T = 1;\r\n else T = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1010",
"desc": "Rm,Rn",
"family": "XOR",
"name": "XOR",
"operands": "(long m, long n)",
"implementation": "XOR(long m, long n) /* XOR Rm,Rn */\r\n{\r\n R[n] ^= R[m];\r\n PC += 2;\r\n}"
},
{
"code": "11001010iiiiiiii",
"desc": "#imm,R0",
"family": "XOR",
"name": "XORI",
"operands": "(long i)",
"implementation": "XORI(long i) /* XOR #imm,R0 */\r\n{\r\n R[0] ^= (0x000000FF & (long)i);\r\n PC += 2;\r\n}"
},
{
"code": "11001110iiiiiiii",
"desc": "#imm,@(R0,GBR)",
"family": "XOR.B",
"name": "XORM",
"operands": "(long i)",
"implementation": "XORM(long i) /* XOR.B #imm,@(R0,GBR) */\r\n{\r\n int temp;\r\n temp = (long)Read_Byte(GBR+R[0]);\r\n temp ^= (0x000000FF &(long)i);\r\n Write_Byte(GBR+R[0],temp);\r\n PC += 2;\r\n}"
},
{
"code": "0010nnnnmmmm1101",
"desc": "Rm,Rn",
"family": "XTRCT",
"name": "XTRCT",
"operands": "(long m, long n)",
"implementation": "XTRCT(long m, long n) /* XTRCT Rm,Rn */\r\n{\r\n unsigned long temp;\r\n temp = (R[m]<<16) & 0xFFFF0000;\r\n R[n] = (R[n]>>16) & 0x0000FFFF;\r\n R[n] |= temp;\r\n PC += 2;\r\n}"
},
{
"code": "1011dddddddddddd",
"desc": "label",
"family": "BSR",
"name": "BSR",
"operands": "(int d)",
"implementation": "BSR(int d) /* BSR disp */\r\n{\r\n int disp;\r\n unsigned int temp;\r\n temp = PC;\r\n if((d&0x800) == 0)\r\n disp = (0x00000FFF & d);\r\n else disp = (0xFFFFF000 | d);\r\n if(is_32bit_instruction(temp+2))\r\n PR = PC + 6;\r\n else PR = PC + 4;\r\n PC = PC + 4 + (disp << 1);\r\n Delay_Slot(temp + 2);\r\n}"
},
{
"code": "0000nnnn00000011",
"desc": "Rn",
"family": "BSRF",
"name": "BSRF",
"operands": "(int n)",
"implementation": "BSRF(int n) /* BSRF Rn */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n if(is_32bit_instruction(temp+2))\r\n PR = PC +6;\r\n else PR = PC + 4;\r\n PC = PC + 4 + R[n];\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0000000010001000",
"desc": "0",
"family": "CLRDMXY",
"name": "CLRDMXY",
"operands": "( )",
"implementation": "CLRDMXY( ) /* CLRDMXY */\r\n{\r\n SR.DMX=0;\r\n SR.DMY=0;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00001011",
"desc": "@Rn",
"family": "JSR",
"name": "JSR",
"operands": "(int n)",
"implementation": "JSR(int n) /* JSR @Rn */\r\n{\r\n unsigned int temp;\r\n temp = PC;\r\n if(is_32bit_instruction(temp+2))\r\n PR = PC +6;\r\n else PR = PC + 4;\r\n PC = R[n];\r\n Delay_Slot(temp+2);\r\n}"
},
{
"code": "0100mmmm00001110",
"desc": "Rm,SR",
"family": "LDC",
"name": "LDCSR",
"operands": "(long m)",
"implementation": "LDCSR(long m) /* LDC Rm,SR : Privileged conditionally */\r\n{\r\n if(SR.MD==1)\r\n {\r\n SR = R[m] & 0x7FFF1FFF;\r\n }\r\n else if(SR.DSP==1)\r\n {\r\n SR = SR & 700003F3 | R[m] & 0x0FFF1C0C;\r\n }\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01011110",
"desc": "LDC",
"family": "LSB",
"name": "LDCMOD",
"operands": "(long m)",
"implementation": "LDCMOD(long m) /* LDC Rm,MOD */\r\n{\r\nMOD = R[m];\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm01111110",
"desc": "Rm,RE",
"family": "LDC",
"name": "LDCRE",
"operands": "(long m)",
"implementation": "LDCRE(long m) /* LDC Rm,RE */\r\n{\r\nRE = R[m];\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm01101110",
"desc": "Rm,RS",
"family": "LDC",
"name": "LDCRS",
"operands": "(long m)",
"implementation": "LDCRS(long m) /* LDC Rm,RS */\r\n{\r\nRS = R[m];\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm00000111",
"desc": "@Rm+,SR",
"family": "LDC.L",
"name": "LDCMSR",
"operands": "(long m)",
"implementation": "LDCMSR(long m)/* LDC.L @Rm+,SR : Privileged conditionally */\r\n{\r\n if(SR.MD==1)\r\n {\r\n SR = Read_Long(R[m]) & 0x7FFF1FFF\r\n }\r\n else if(SR.DSP==1)\r\n {\r\n SR = SR & 700003F3 | Read_Long(R[m]) & 0x0FFF1C0C;\r\n }\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01010111",
"desc": "LDC.L",
"family": "LSB",
"name": "LDCMMOD",
"operands": "(long m)",
"implementation": "LDCMMOD(long m)/*LDC.L @Rm+,MOD */\r\n{\r\nMOD = Read_Long(R[m]);\r\nR[m] += 4;\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm01110111",
"desc": "@Rm+,RE",
"family": "LDC.L",
"name": "LDCMRE",
"operands": "(long m)",
"implementation": "LDCMRE(long m) /*LDC.L @Rm+,RE */\r\n{\r\nRE = Read_Long(R[m]);\r\nR[m] += 4;\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm01100111",
"desc": "@Rm+,RS",
"family": "LDC.L",
"name": "LDCMRS",
"operands": "(long m)",
"implementation": "LDCMRS(long m) /*LDC.L @Rm+,RS */\r\n{\r\nRS = Read_Long(R[m]);\r\nR[m] += 4;\r\nPC += 2;\r\n}"
},
{
"code": "0100mmmm00110100",
"desc": "Rm",
"family": "LDRC",
"name": "LDRC",
"operands": "(long m)",
"implementation": "LDRC(long m) /* LDRC Rm*/\r\n{\r\n long temp;\r\n temp = (R[m] & 0x00000FFF)<<16;\r\n SR &= 0xF000FFFF;\r\n SR |= temp;\r\n RF1 = Repeat_Control_Flag1;\r\n RF0 = Repeat_Control_Flag0;\r\n PC += 2;\r\n RE[0] = 1;\r\n}"
},
{
"code": "10001010iiiiiiii",
"desc": "#imm",
"family": "LDRC",
"name": "LDRCI",
"operands": "(long i)",
"implementation": "LDRCI(long i) /* LDRC #imm*/\r\n{\r\n long temp;\r\n temp = (R[m] & 0x000000FF)<<16;\r\n SR &= 0xF000FFFF;\r\n SR |= temp;\r\n RF1 = Repeat_Control_Flag1;\r\n RF0 = Repeat_Control_Flag0;\r\n PC += 2;\r\n RE[0] = 1;\r\n}"
},
{
"code": "10001110dddddddd",
"desc": "@(disp*,PC)",
"family": "LDRE",
"name": "LDRE",
"operands": "(long d)",
"implementation": "LDRE(long d) /* LDRE @(disp, PC) */\r\n{\r\n long disp;\r\n if ((d&0x80)==0) disp = (0x000000FF & (long)d);\r\n else disp = (0xFFFFFF00 | (long)d);\r\n RE = PC + (disp<<1);\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01101010",
"desc": "Rm,DSR",
"family": "LDS",
"name": "LDSDSR",
"operands": "(long m)",
"implementation": "LDSDSR(long m) /* LDS Rm,DSR */\r\n{\r\n DSR = R[m] & 0x0000000F;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01111010",
"desc": "Rm,A0",
"family": "LDS",
"name": "LDSA0",
"operands": "(long m)",
"implementation": "LDSA0(long m) /* LDS Rm,A0 */\r\n{\r\n A0 = R[m];\r\n if((A0&0x80000000) == 0) A0G = 0x00;\r\n else A0G = 0xFF;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm10001010",
"desc": "Rm,X0",
"family": "LDS",
"name": "LDSX0",
"operands": "(long m)",
"implementation": "LDSX0(long m) /* LDS Rm,X0 */\r\n{\r\n X0 = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm10011010",
"desc": "Rm,X1",
"family": "LDS",
"name": "LDSX1",
"operands": "(long m)",
"implementation": "LDSX1(long m) /* LDS Rm,X1 */\r\n{\r\n X1 = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm10101010",
"desc": "Rm,Y0",
"family": "LDS",
"name": "LDSY0",
"operands": "(long m)",
"implementation": "LDSY0(long m) /* LDS Rm,Y0 */\r\n{\r\n Y0 = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm10111010",
"desc": "Rm,Y1",
"family": "LDS",
"name": "LDSY1",
"operands": "(long m)",
"implementation": "LDSY1(long m) /* LDS Rm,Y1 */\r\n{\r\n Y1 = R[m];\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01100110",
"desc": "@Rm+,DSR",
"family": "LDS.L",
"name": "LDSMDSR",
"operands": "(long m)",
"implementation": "LDSMDSR(long m) /* LDS.L @Rm+,DSR */\r\n{\r\n DSR = Read_Long(R[m])&0x0000000F;\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm01110110",
"desc": "@Rm+,A0",
"family": "LDS.L",
"name": "LDSMA0",
"operands": "(long m)",
"implementation": "LDSMA0(long m) /* LDS.L @Rm+,A0 */\r\n{\r\n A0 = Read_Long(R[m]);\r\n if ((A0&0x80000000) == 0) A0G = 0x00;\r\n else A0G = 0xFF;\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10000110",
"desc": "@Rm+,X0",
"family": "LDS.L",
"name": "LDSMX0",
"operands": "(long m)",
"implementation": "LDSMX0(long m) /* LDS.L @Rm+,X0 */\r\n{\r\n X0 = Read_Long (R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10010110",
"desc": "@Rm+,X1",
"family": "LDS.L",
"name": "LDSMX1",
"operands": "(long m)",
"implementation": "LDSMX1(long m) /* LDS.L @Rm+,X1 */\r\n{\r\n X1 = Read_Long (R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10100110",
"desc": "@Rm+,Y0",
"family": "LDS.L",
"name": "LDSMY0",
"operands": "(long m)",
"implementation": "LDSMY0(long m) /* LDS.L @Rm+,Y0 */\r\n{\r\n Y0 = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10110110",
"desc": "@Rm+,Y1",
"family": "LDS.L",
"name": "LDSMY1",
"operands": "(long m)",
"implementation": "LDSMY1(long m) /* LDS.L @Rm+,Y1 */\r\n{\r\n Y1 = Read_Long(R[m]);\r\n R[m] += 4;\r\n PC += 2;\r\n}"
},
{
"code": "10001100dddddddd",
"desc": "@(disp*,PC)",
"family": "LDRS",
"name": "LDRS",
"operands": "(long d)",
"implementation": "LDRS(long d) /* LDRS @(disp, PC) */\r\n{\r\n long disp;\r\n if ((d&0x80)==0) disp = (0x000000FF & (long)d);\r\n else disp = (0xFFFFFF00 | (long)d);\r\n RS = PC + (disp<<1);\r\n PC += 2;\r\n}"
},
{
"code": "0000000010011000",
"desc": "1",
"family": "SETDMX",
"name": "SETDMX",
"operands": "( )",
"implementation": "SETDMX( ) /* SETDMX */\r\n{\r\n SR.DMX = 1;\r\n SR.DMY = 0;\r\n PC += 2;\r\n}"
},
{
"code": "0000000011001000",
"desc": "0",
"family": "SETDMX",
"name": "SETDMY",
"operands": "( )",
"implementation": "SETDMY( ) /* SETDMY */\r\n{\r\n SR.DMX = 0;\r\n SR.DMY = 1;\r\n PC += 2;\r\n}"
},
{
"code": "0100mmmm00010100",
"desc": "Rm",
"family": "SETRC",
"name": "SETRC",
"operands": "(long m)",
"implementation": "SETRC(long m) /* SETRC Rm */\r\n{\r\n long temp;\r\n temp = (R[m] & 0x00000FFF)<<16;\r\n SR &= 0xF000FFFF;\r\n SR |= temp;\r\n RF1 = Repeat_Control_Flag1;\r\n RF0 = Repeat_Control_Flag0;\r\n PC += 2;\r\n}"
},
{
"code": "10000010iiiiiiii",
"desc": "#imm",
"family": "SETRC",
"name": "SETRCI",
"operands": "(long i)",
"implementation": "SETRCI(long i) /* SETRC #imm */\r\n{\r\n long temp;\r\n temp = ((long)i & 0x000000FF) << 16;\r\n SR &= 0xF000FFFF;\r\n SR |= temp;\r\n RF1 = Repeat_Control_Flag1;\r\n RF0 = Repeat_Control_Flag0;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn00000010",
"desc": "SR,Rn",
"family": "STC",
"name": "STCSR",
"operands": "(long n)",
"implementation": "STCSR(long n) /*STC SR,Rn */\r\n{\r\n R[n] = SR;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn01010010",
"desc": "MOD,Rn",
"family": "STC",
"name": "STCMOD",
"operands": "(long n)",
"implementation": "STCMOD(long n) /* STC MOD,Rn */\r\n{\r\n R[n] = MOD\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn01110010",
"desc": "RE,Rn",
"family": "STC",
"name": "STCRE",
"operands": "(long n)",
"implementation": "STCRE(long n) /* STC RE, Rn */\r\n{\r\n R[n] = RE;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn01100010",
"desc": "RS,Rn",
"family": "STC",
"name": "STCRS",
"operands": "(long n)",
"implementation": "STCRS(long n) /* STC RS,Rn */\r\n{\r\n R[n] = RS;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn00000011",
"desc": "SR,@-Rn",
"family": "STC.L",
"name": "STCMSR",
"operands": "(long n)",
"implementation": "STCMSR(long n) /* STC.L SR,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long (R[n],SR);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn01010011",
"desc": "MOD,@-Rn",
"family": "STC.L",
"name": "STCMMOD",
"operands": "(long n)",
"implementation": "STCMMOD(long n) /* STC.L MOD,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long (R[n],MOD);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn01110011",
"desc": "RE,@-Rn",
"family": "STC.L",
"name": "STCMRE",
"operands": "(long n)",
"implementation": "STCMRE(long n) /* STC.L RE,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long (R[n],RE);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn01100011",
"desc": "RS,@-Rn",
"family": "STC.L",
"name": "STCMRS",
"operands": "(long n)",
"implementation": "STCMRS(long n) /* STC.L RS, @-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long (R[n],RS);\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn01101010",
"desc": "DSR,Rn",
"family": "STS",
"name": "STSDSR",
"operands": "(long n)",
"implementation": "STSDSR (long n) /* STS DSR,Rn */\r\n{\r\n R[n] = DSR;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn01111010",
"desc": "A0,Rn",
"family": "STS",
"name": "STSA0",
"operands": "(long n)",
"implementation": "STSA0 (long n) /* STS A0,Rn */\r\n{\r\n R[n] = A0;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10001010",
"desc": "X0,Rn",
"family": "STS",
"name": "STSX0",
"operands": "(long n)",
"implementation": "STSX0 (long n) /* STS X0,Rn */\r\n{\r\n R[n] = X0;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10011010",
"desc": "X1,Rn",
"family": "STS",
"name": "STSX1",
"operands": "(long n)",
"implementation": "STSX1(long n) /* STS X1,Rn */\r\n{\r\n R[n] = X1;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10101010",
"desc": "Y0,Rn",
"family": "STS",
"name": "STSY0",
"operands": "(long n)",
"implementation": "STSY0(long n) /* STS Y0,Rn */\r\n{\r\n R[n] = Y0;\r\n PC += 2;\r\n}"
},
{
"code": "0000nnnn10111010",
"desc": "Y1,Rn",
"family": "STS",
"name": "STSY1",
"operands": "(long n)",
"implementation": "STSY1(long n) /* STS Y1,Rn */\r\n{\r\n R[n] = Y1;\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn01100010",
"desc": "DSR,@–Rn",
"family": "STS.L",
"name": "STSMDSR",
"operands": "(long n)",
"implementation": "STSMDSR(long n) /* STS.L DSR,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],DSR);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn01110010",
"desc": "A0,@–Rn",
"family": "STS.L",
"name": "STSMA0",
"operands": "(long n)",
"implementation": "STSMA0(long n) /* STS.L A0,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],A0);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10000010",
"desc": "X0,@-Rn",
"family": "STS.L",
"name": "STSMX0",
"operands": "(long n)",
"implementation": "STSMX0(long n) /* STS.L X0,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],X0);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10010010",
"desc": "X1,@-Rn",
"family": "STS.L",
"name": "STSMX1",
"operands": "(long n)",
"implementation": "STSMX1(long n) /* STS.L X1,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],X1);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10100010",
"desc": "Y0,@-Rn",
"family": "STS.L",
"name": "STSMY0",
"operands": "(long n)",
"implementation": "STSMY0(long n) /* STS.L Y0,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],Y0);\r\n PC += 2;\r\n}"
},
{
"code": "0100nnnn10110010",
"desc": "Y1,@-Rn",
"family": "STS.L",
"name": "STSMY1",
"operands": "(long n)",
"implementation": "STSMY1(long n) /* STS.L Y1,@-Rn */\r\n{\r\n R[n] -= 4;\r\n Write_Long(R[n],Y1);\r\n PC += 2;\r\n}"
}
]
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