fx9860-emulator-playground/scripts/raw_instructions.txt

Format Operation Instruction Code Cycle T Bit
ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 1 —
ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii 1 —
Description: This instruction adds together the contents of general registers Rn and Rm and stores
the result in Rn.
8-bit immediate data can also be added to the contents of general register Rn.
8-bit immediate data is sign-extended to 32 bits, allowing use in decrement operations.
Notes: None
Operation:
ADD(long m, long n) /* ADD Rm,Rn */
{
 R[n] += R[m];
 PC += 2;
}
ADDI(long i, long n) /* ADD #imm,Rn */
{
 if ((i&0x80)==0)
 R[n] += (0x000000FF & (long)i);
 else R[n] += (0xFFFFFF00 | (long)i);
 PC += 2;
}
Example:
ADD R0,R1 ;Before execution R0 = H'7FFFFFFF, R1 = H'00000001
 ;After execution R1 = H'80000000
ADD #H'01,R2 ;Before execution R2 = H'00000000
 ;After execution R2 = H'00000001
ADD #H'FE,R3 ;Before execution R3 = H'00000001
 ;After execution R3 = H'FFFFFFFF
Rev. 1.50, 10/04, page 295 of 610
11.1.2 ADDC (Add with Carry): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
ADDC Rm,Rn Rn + Rm + T → Rn,
carry → T
0011nnnnmmmm1110 1 Carry
Description: This instruction adds together the contents of general registers Rn and Rm and the T
bit, and stores the result in Rn. A carry resulting from the operation is reflected in the T bit. This
instruction is used for additions exceeding 32 bits.
Notes: None
Operation:
ADDC(long m, long n) /* ADDC Rm,Rn */
{
 unsigned long tmp0,tmp1;
 tmp1 = R[n] + R[m];
 tmp0 = R[n];
 R[n] = tmp1 + T;
 if (tmp0>tmp1) T = 1;
 else T = 0;
 if (tmp1>R[n]) T = 1;
 PC += 2;
}
Example:
CLRT ;R0:R1(64 bits) + R2:R3(64 bits) = R0:R1(64 bits)
ADDC R3,R1 ;Before execution T = 0, R1 = H'00000001, R3 = H'FFFFFFFF
 ;After execution T = 1, R1 = H'00000000
ADDC R2,R0 ;Before execution T = 1, R0 = H'00000000, R2 = H'00000000
 ;After execution T = 0, R0 = H'00000001
Rev. 1.50, 10/04, page 296 of 610
11.1.3 ADDV (Add with (V flag) Overflow Check): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
ADDV Rm,Rn Rn + Rm → Rn,
overflow → T
0011nnnnmmmm1111 1 Overflow
Description:This instruction adds together the contents of general registers Rn and Rm and stores
the result in Rn. If overflow occurs, the T bit is set.
Notes: None
Operation:
ADDV(long m, long n) /* ADDV Rm,Rn */
{
 long dest,src,ans;
 if ((long)R[n]>=0) dest = 0;
 else dest = 1;
 if ((long)R[m]>=0) src = 0;
 else src = 1;
 src += dest;
 R[n] += R[m];
 if ((long)R[n]>=0) ans = 0;
 else ans = 1;
 ans += dest;
 if (src==0 || src==2) {
 if (ans==1) T = 1;
 else T = 0;
 }
 else T = 0;
 PC += 2;
}
Rev. 1.50, 10/04, page 297 of 610
Example:
ADDV R0,R1 ;Before execution R0 = H'00000001, R1 = H'7FFFFFFE, T=0
 ;After execution R1 = H'7FFFFFFF, T=0
ADDV R0,R1 ;Before execution R0 = H'00000002, R1 = H'7FFFFFFE, T=0
 ;After execution R1 = H'80000000, T=1
Rev. 1.50, 10/04, page 298 of 610
11.1.4 AND (AND Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 1 —
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1 —
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →
(R0 + GBR)
11001101iiiiiiii 3 —
Description:This instruction ANDs the contents of general registers Rn and Rm and stores the
result in Rn.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data.
Notes: With AND #imm,R0, the upper 24 bits of R0 are always cleared as a result of the
operation.
Operation:
AND(long m, long n) /* AND Rm,Rn */
{
 R[n] &= R[m];
 PC += 2;
}
ANDI(long i) /* AND #imm,R0 */
{
 R[0] &= (0x000000FF & (long)i);
 PC += 2;
}
ANDM(long i) /* AND.B #imm,@(R0,GBR) */
{
 long temp;
 temp = (long)Read_Byte(GBR+R[0]);
Rev. 1.50, 10/04, page 299 of 610
 temp &= (0x000000FF & (long)i);
 Write_Byte(GBR+R[0],temp);
 PC += 2;
}
Example:
 AND R0,R1 ;Before execution R0 = H'AAAAAAAA, R1=H'55555555
 ;After execution R1 = H'00000000
 AND #H'0F,R0 ;Before execution R0 = H'FFFFFFFF
 ;After execution R0 = H'0000000F
 AND.B #H'80,@(R0,GBR) ;Before execution (R0,GBR) = H'A5
 ;After execution (R0,GBR) = H'80
Possible Exceptions: Exceptions may occur when AND.B instruction is executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Exceptions are checked taking a data access by this instruction as a byte load and a byte store.
Rev. 1.50, 10/04, page 300 of 610
11.1.5 BF (Branch if False): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BF label If T = 0
PC + 4 + disp × 2 → PC
If T = 1, nop
10001011dddddddd 1 —
Description: This is a conditional branch instruction that references the T bit. The branch is taken
if T = 0, and not taken if T = 1. The branch destination is address (PC + 4 + displacement × 2).
The PC source value is the BF instruction address. As the 8-bit displacement is multiplied by two
after sign-extension, the branch destination can be located in the range from –256 to +254 bytes
from the BF instruction.
Notes: If the branch destination cannot be reached, the branch must be handled by using BF in
combination with a BRA or JMP instruction, for example.
Operation:
BF(int d) /* BF disp */
{
 int disp;
 if ((d&0x80)==0)
 disp = (0x000000FF & d);
 else disp = (0xFFFFFF00 | d);
 if (T==0)
 PC = PC+4+(disp<<1);
 else PC += 2;
}
Example:
 CLRT ;Normally T = 0
 BT TRGET_T ;T = 0, so branch is not taken.
 BF TRGET_F ;T = 0, so branch to TRGET_F.
 NOP ;
 NOP ;
TRGET_F: ;← BF instruction branch destination
Rev. 1.50, 10/04, page 301 of 610
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 302 of 610
11.1.6 BF/S (Branch if False with Delay Slot): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BF/S label If T = 0,
PC + 4 + disp × 2 → PC
If T = 1, nop
10001111dddddddd 1 —
Description: This is a delayed conditional branch instruction that references the T bit. If T = 1, the
next instruction is executed and the branch is not taken. If T = 0, the branch is taken after
execution of the next instruction.
The branch destination is address (PC + 4 + displacement × 2). The PC source value is the BF/S
instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from –256 to +254 bytes from the BF/S instruction.
Notes: As this is a delayed branch instruction, when the branch condition is satisfied, the
instruction following this instruction is executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction.
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.
If this instruction is located in the delay slot immediately following a delayed branch instruction, it
is identified as a slot illegal instruction.
If the branch destination cannot be reached, the branch must be handled by using BF/S in
combination with a BRA or JMP instruction, for example.
Rev. 1.50, 10/04, page 303 of 610
Operation:
BFS(int d) /* BFS disp */
{
 int disp;
 unsigned int temp;
 temp = PC;
 if ((d&0x80)==0)
 disp = (0x000000FF & d);
 else disp = (0xFFFFFF00 | d);
 if (T==0)
 PC = PC + 4 + (disp<<1);
 else PC += 4;
 Delay_Slot(temp+2);
}
Example:
 CLRT ;Normally T = 0
 BT/S TRGET_T ;T = 0, so branch is not taken.
 NOP ;
 BF/S TRGET_F ;T = 0, so branch to TRGET.
 ADD R0,R1 ;Executed before branch.
 NOP ;
TRGET_F: ;← BF/S instruction branch destination
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 304 of 610
11.1.7 BRA (Branch): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BRA label PC + 4 + disp × 2 → PC 1010dddddddddddd 1 —
Description: This is an unconditional branch instruction. The branch destination is address (PC +
4 + displacement × 2). The PC source value is the BRA instruction address. As the 12-bit
displacement is multiplied by two after sign-extension, the branch destination can be located in the
range from –4096 to +4094 bytes from the BRA instruction. If the branch destination cannot be
reached, this branch can be performed with a JMP instruction.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
BRA(int d) /* BRA disp */
{
 int disp;
 unsigned int temp;
 temp = PC;
 if ((d&0x800)==0)
 disp = (0x00000FFF & d);
 else disp = (0xFFFFF000 | d);
 PC = PC + 4 + (disp<<1);
 Delay_Slot(temp+2);
}
Example:
 BRA TRGET ;Branch to TRGET.
 ADD R0,R1 ;ADD executed before branch.
 NOP ;
TRGET: ;← BRA instruction branch destination
Rev. 1.50, 10/04, page 305 of 610
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 306 of 610
11.1.8 BRAF (Branch Far): Branch Instruction (Delayed Branch Instruction)
Format Operation Instruction Code Cycle T Bit
BRAF Rn PC + 4 + Rn → PC 0000nnnn00100011 1 —
Description: This is an unconditional branch instruction. The branch destination is address (PC +
4 + Rn). The branch destination address is the result of adding 4 plus the 32-bit contents of general
register Rn to PC.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
BRAF(int n) /* BRAF Rn */
{
 unsigned int temp;
 temp = PC;
 PC = PC + 4 + R[n];
 Delay_Slot(temp+2);
}
Example:
 MOV.L #(TRGET-BRAF_PC),R0 ;Set displacement.
 BRAF R0 ;Branch to TRGET.
 ADD R0,R1 ;ADD executed before branch.
 BRAF_PC: ;
 NOP
 TRGET: ;← BRAF instruction branch destination
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 307 of 610
11.1.9 BT (Branch if True): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BT label If T = 1
PC + 4 + disp × 2 → PC
If T = 0, nop
10001001dddddddd 1 —
Description: This is a conditional branch instruction that references the T bit. The branch is taken
if T = 1, and not taken if T = 0.
The branch destination is address (PC + 4 + displacement × 2). The PC source value is the BT
instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from –256 to +254 bytes from the BT instruction.
Notes: If the branch destination cannot be reached, the branch must be handled by using BT in
combination with a BRA or JMP instruction, for example.
Operation:
BT(int d) /* BT disp */
{
 int disp;
 if ((d&0x80)==0)
 disp = (0x000000FF & d);
 else disp = (0xFFFFFF00 | d);
 if (T==1)
 PC = PC + 4 + (disp<<1);
 else PC += 2;
}
Example:
 SETT ;Normally T = 1
 BF TRGET_F ;T = 1, so branch is not taken.
 BT TRGET_T ;T = 1, so branch to TRGET_T.
 NOP ;
 NOP ;
TRGET_T: ;← BT instruction branch destination
Rev. 1.50, 10/04, page 308 of 610
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 309 of 610
11.1.10 BT/S (Branch if True with Delay Slot): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BT/S label If T = 1,
PC + 4 + disp × 2 → PC
If T = 0, nop
10001101dddddddd 1 —
Description: This is a conditional branch instruction that references the T bit. The branch is taken
if T = 1, and not taken if T = 0.
The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by
two after sign-extension, the branch destination can be located in the range from –256 to +254
bytes from the BT/S instruction.
Notes: As this is a delayed branch instruction, when the branch condition is satisfied, the
instruction following this instruction is executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction.
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.
If the branch destination cannot be reached, the branch must be handled by using BT/S in
combination with a BRA or JMP instruction, for example.
Operation:
BTS(int d) /* BTS disp */
{
 int disp;
 unsigned temp;
 temp = PC;
 if ((d&0x80)==0)
 disp = (0x000000FF & d);
 else disp = (0xFFFFFF00 | d);
 if (T==1)
 PC = PC + 4 + (disp<<1);
 else PC += 4;
 Delay_Slot(temp+2);
}
Rev. 1.50, 10/04, page 310 of 610
Example:
 SETT ;Normally T = 1
 BF/S TRGET_F ;T = 1, so branch is not taken.
 NOP ;
 BT/S TRGET_T ;T = 1, so branch to TRGET_T.
 ADD R0,R1 ;Executed before branch.
 NOP ;
TRGET_T: ;← BT/S instruction branch destination
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 311 of 610
11.1.11 CLRMAC (Clear MAC Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
CLRMAC 0 → MACH, MACL 0000000000101000 1 —
Description: This instruction clears the MACH and MACL registers.
Notes: None
Operation:
CLRMAC( ) /* CLRMAC */
{
 MACH = 0;
 MACL = 0;
 PC += 2;
}
Example:
 CLRMAC ;Clear MAC register to initialize.
 MAC.W @R0+,@R1+ ;Multiply-and-accumulate operation
 MAC.W @R0+,@R1+ ;
Rev. 1.50, 10/04, page 312 of 610
11.1.12 CLRS (Clear S Bit): System Control Instruction
Format Operation Instruction Code Cycle T Bit
CLRS 0 → S 0000000001001000 1 —
Description: This instruction clears the S bit to 0.
Notes: None
Operation:
CLRS( ) /* CLRS */
{
 S = 0;
 PC += 2;
}
Example:
CLRS ;Before execution S = 1
 ;After execution S = 0
Rev. 1.50, 10/04, page 313 of 610
11.1.13 CLRT (Clear T Bit): System Control Instruction
Format Operation Instruction Code Cycle T Bit
CLRT 0 → T 0000000000001000 1 0
Description: This instruction clears the T bit.
Notes: None
Operation:
CLRT( ) /* CLRT */
{
 T = 0;
 PC += 2;
}
Example:
CLRT ;Before execution T = 1
 ;After execution T = 0
Rev. 1.50, 10/04, page 314 of 610
11.1.14 CMP/cond (Compare Conditionally): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
CMP/EQ Rm,Rn If Rn = Rm, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0000 1 Result of
comparison
CMP/GE Rm,Rn If Rn ≥ Rm, signed, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0011 1 Result of
comparison
CMP/GT Rm,Rn If Rn > Rm, signed, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0111 1 Result of
comparison
CMP/HI Rm,Rn If Rn > Rm, unsigned, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0110 1 Result of
comparison
CMP/HS Rm,Rn If Rn ≥ Rm, unsigned, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0010 1 Result of
comparison
CMP/PL Rn If Rn > 0, 1 → T
Otherwise, 0 → T
0100nnnn00010101 1 Result of
comparison
CMP/PZ Rn If Rn ≥ 0, 1 → T
Otherwise, 0 → T
0100nnnn00010001 1 Result of
comparison
CMP/STR Rm,Rn If any bytes are equal, 1 → T
Otherwise, 0 → T
0010nnnnmmmm1100 1 Result of
comparison
CMP/EQ #imm,R0 If R0 = imm, 1 → T
Otherwise, 0 → T
10001000iiiiiiii 1 Result of
comparison
Description: This instruction compares general registers Rn and Rm, and sets the T bit if the
specified condition (cond) is true. If the condition is false, the T bit is cleared. The contents of Rn
are not changed. Nine conditions can be specified. For the two conditions PZ and PL, Rn is
compared with 0.
With the EQ condition, sign-extended 8-bit immediate data can be compared with R0. The
contents of R0 are not changed.
Rev. 1.50, 10/04, page 315 of 610
Mnemonic Description
CMP/EQ Rm,Rn If Rn = Rm, T = 1
CMP/GE Rm,Rn If Rn ≥ Rm as signed values, T = 1
CMP/GT Rm,Rn If Rn > Rm as signed values, T = 1
CMP/HI Rm,Rn If Rn > Rm as unsigned values, T = 1
CMP/HS Rm,Rn If Rn ≥ Rm as unsigned values, T = 1
CMP/PL Rn If Rn > 0, T = 1
CMP/PZ Rn If Rn ≥ 0, T = 1
CMP/STR Rm,Rn If any bytes are equal, T = 1
CMP/EQ #imm,R0 If R0 = imm, T = 1
Notes: None
Operation:
CMPEQ(long m, long n) /* CMP_EQ Rm,Rn */
{
 if (R[n]==R[m]) T = 1;
 else T = 0;
 PC += 2;
}
CMPGE(long m, long n) /* CMP_GE Rm,Rn */
{
 if ((long)R[n]>=(long)R[m]) T = 1;
 else T = 0;
 PC += 2;
}
CMPGT(long m, long n) /* CMP_GT Rm,Rn */
{
 if ((long)R[n]>(long)R[m]) T = 1;
 else T = 0;
 PC += 2;
}
Rev. 1.50, 10/04, page 316 of 610
CMPHI(long m, long n) /* CMP_HI Rm,Rn */
{
 if ((unsigned long)R[n]>(unsigned long)R[m]) T = 1;
 else T = 0;
 PC += 2;
}
CMPHS(long m, long n) /* CMP_HS Rm,Rn */
{
 if ((unsigned long)R[n]>=(unsigned long)R[m]) T = 1;
 else T = 0;
 PC += 2;
}
CMPPL(long n) /* CMP_PL Rn */
{
 if ((long)R[n]>0) T = 1;
 else T = 0;
 PC += 2;
}
CMPPZ(long n) /* CMP_PZ Rn */
{
 if ((long)R[n]>=0) T = 1;
 else T = 0;
 PC += 2;
}
Rev. 1.50, 10/04, page 317 of 610
CMPSTR(long m, long n) /* CMP_STR Rm,Rn */
{
 unsigned long temp;
 long HH,HL,LH,LL;
 temp=R[n]^R[m];
 HH = (temp & 0xFF000000) >> 24;
 HL = (temp & 0x00FF0000) >> 16;
 LH = (temp & 0x0000FF00) >> 8;
 LL = temp & 0x000000FF;
 HH = HH && HL && LH && LL;
 if (HH==0) T = 1;
 else T = 0;
 PC += 2;
}
CMPIM(long i) /* CMP_EQ #imm,R0 */
{
 long imm;
 if ((i&0x80)==0) imm=(0x000000FF & (long) i);
 else imm=(0xFFFFFF00 | (long) i);
 if (R[0]==imm) T = 1;
 else T = 0;
 PC += 2;
}
Example:
CMP/GE R0,R1 ;R0 = H'7FFFFFFF, R1 = H'80000000
BT TRGET_T ;T = 0, so branch is not taken.
CMP/HS R0,R1 ;R0 = H'7FFFFFFF, R1 = H'80000000
BT TRGET_T ;T = 1, so branch is taken.
CMP/STR R2,R3 ;R2 = "ABCD", R3 = "XYCZ"
BT TRGET_T ;T = 1, so branch is taken.
Rev. 1.50, 10/04, page 318 of 610
11.1.15 DIV0S (Divide (Step 0) as Signed): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DIV0S Rm,Rn MSB of Rn → Q,
MSB of Rm → M,
M^Q → T
0010nnnnmmmm0111 1 Result of
calculation
Description: This instruction performs initial settings for signed division. This instruction is
followed by a DIV1 instruction that executes 1-digit division, for example, and repeated divisions
are executed to find the quotient. See the description of the DIV1 instruction for details.
Notes: None
Operation:
DIV0S(long m, long n) /* DIV0S Rm,Rn */
{
 if ((R[n] & 0x80000000)==0) Q = 0;
 else Q = 1;
 if ((R[m] & 0x80000000)==0) M = 0;
 else M = 1;
 T = !(M==Q);
 PC += 2;
}
Example:
See the examples for the DIV1 instruction.
Rev. 1.50, 10/04, page 319 of 610
11.1.16 DIV0U (Divide (Step 0) as Unsigned): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DIV0U 0 → M/Q/T 0000000000011001 1 0
Description: This instruction performs initial settings for unsigned division. This instruction is
followed by a DIV1 instruction that executes 1-digit division, for example, and repeated divisions
are executed to find the quotient. See the description of the DIV1 instruction for details.
Notes: None
Operation:
DIV0U( ) /* DIV0U */
{
 M = Q = T = 0;
 PC += 2;
}
Example:
See the examples for the DIV1 instruction.
Rev. 1.50, 10/04, page 320 of 610
11.1.17 DIV1 (Divide 1 Step): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DIV1 Rm,Rn 1-step division
(Rn ÷ Rm)
0011nnnnmmmm0100 1 Result of
calculation
Description: This instruction performs 1-digit division (1-step division) of the 32-bit contents of
general register Rn (dividend) by the contents of Rm (divisor). The quotient is obtained by
repeated execution of this instruction alone or in combination with other instructions. The
specified registers and the M, Q, and T bits must not be modified during these repeated
executions.
In 1-step division, the dividend is shifted 1 bit to the left, the divisor is subtracted from this, and
the quotient bit is reflected in the Q bit according to whether the result is positive or negative.
The remainder can be found as follows after first finding the quotient using the DIV1 instruction:
(Remainder) = (dividend) – (divisor) × (quotient)
Detection of division by zero or overflow is not provided. Check for division by zero and overflow
division before executing the division. A remainder operation is not provided. Find the remainder
by finding the product of the divisor and the obtained quotient, and subtracting this value from the
dividend.
Initial settings should first be made with the DIV0S or DIV0U instruction. DIV1 is executed once
for each bit of the divisor. If a quotient of more than 17 bits is required, place an ROTCL
instruction before the DIV1 instruction. See the examples for details of the division sequence.
Notes: None
Rev. 1.50, 10/04, page 321 of 610
Operation:
DIV1(long m, long n) /* DIV1 Rm,Rn */
{
 unsigned long tmp0, tmp2;
 unsigned char old_q, tmp1;
 old_q = Q;
 Q = (unsigned char)((0x80000000 & R[n])!=0);
 tmp2 = R[m];
 R[n] <<= 1;
 R[n] |= (unsigned long)T;
 switch(old_q){
 case 0:switch(M){
 case 0:tmp0 = R[n];
 R[n] -= tmp2;
 tmp1 = (R[n]>tmp0);
 switch(Q){
 case 0:Q = tmp1;
 break;
 case 1:Q = (unsigned char)(tmp1==0);
 break;
 }
 break;
 case 1:tmp0 = R[n];
 R[n] += tmp2;
 tmp1 = (R[n]<tmp0);
 switch(Q){
 case 0:Q = (unsigned char)(tmp1==0);
 break;
 case 1:Q = tmp1;
 break;
 }
 break;
 }
Rev. 1.50, 10/04, page 322 of 610
 break;
 case 1:switch(M){
 case 0:tmp0 = R[n];
 R[n] += tmp2;
 tmp1 = (R[n]<tmp0);
 switch(Q){
 case 0:Q = tmp1;
 break;
 case 1:Q = (unsigned char)(tmp1==0);
 break;
 }
 break;
 case 1:tmp0 = R[n];
 R[n] -= tmp2;
 tmp1 = (R[n]>tmp0);
 switch(Q){
 case 0:Q = (unsigned char)(tmp1==0);
 break;
 case 1:Q = tmp1;
 break;
 }
 break;
 }
 break;
 }
 T = (Q==M);
 PC += 2;
}
Rev. 1.50, 10/04, page 323 of 610
Example 1:
 ;R1 (32 bits) ÷ R0 (16 bits) = R1 (16 bits); unsigned
SHLL16 R0 ;Set divisor in upper 16 bits, clear lower 16 bits to 0
TST R0,R0 ;Check for division by zero
BT ZERO_DIV ;
CMP/HS R0,R1 ;Check for overflow
BT OVER_DIV ;
DIV0U ;Flag initialization
.arepeat 16 ;
DIV1 R0,R1 ;Repeat 16 times
.aendr ;
ROTCL R1 ;
EXTU.W R1,R1 ;R1 = quotient
Example 2:
 ; R1:R2 (64 bits) ÷ R0 (32 bits) = R2 (32 bits); unsigned
TST R0,R0 ;Check for division by zero
BT ZERO_DIV ;
CMP/HS R0,R1 ;Check for overflow
BT OVER_DIV ;
DIV0U ;Flag initialization
.arepeat 32 ;
ROTCL R2 ;Repeat 32 times
DIV1 R0,R1 ;
.aendr ;
ROTCL R2 ;R2 = quotient
Rev. 1.50, 10/04, page 324 of 610
Example 3:
 ;R1 (16 bits) ÷ R0 (16 bits) = R1 (16 bits); signed
SHLL16 R0 ;Set divisor in upper 16 bits, clear lower 16 bits to 0
EXTS.W R1,R1 ;Dividend sign-extended to 32 bits
XOR R2,R2 ;R2 = 0
MOV R1,R3 ;
ROTCL R3 ;
SUBC R2,R1 ;If dividend is negative, subtract 1
DIV0S R0,R1 ;Flag initialization
.arepeat 16 ;
DIV1 R0,R1 ;Repeat 16 times
.aendr ;
EXTS.W R1,R1 ;
ROTCL R1 ;R1 = quotient (one's complement notation)
ADDC R2,R1 ;If MSB of quotient is 1, add 1 to convert to two's complement notation
EXTS.W R1,R1 ;R1 = quotient (two's complement notation)
Example 4:
 ;R2 (32 bits) ÷ R0 (32 bits) = R2 (32 bits); signed
MOV R2,R3 ;
ROTCL R3 ;
SUBC R1,R1 ;Dividend sign-extended to 64 bits (R1:R2)
XOR R3,R3 ;R3 = 0
SUBC R3,R2 ;If dividend is negative, subtract 1 to convert to one's complement notation
DIV0S R0,R1 ;Flag initialization
.arepeat 32 ;
ROTCL R2 ;Repeat 32 times
DIV1 R0,R1 ;
.aendr ;
ROTCL R2 ;R2 = quotient (one's complement notation)
ADDC R3,R2 ;If MSB of quotient is 1, add 1 to convert to two's complement notation
 ;R2 = quotient (two's complement notation)
Rev. 1.50, 10/04, page 325 of 610
11.1.18 DMULS.L (Double-length Multiply as Signed): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DMULS.L Rm,Rn Signed,
Rn × Rm →MAC
0011nnnnmmmm1101 2 —
Description: This instruction performs 32-bit multiplication of the contents of general register Rn
by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The
multiplication is performed as a signed arithmetic operation.
Notes: None
Operation:
DMULS(long m, long n) /* DMULS.L Rm,Rn */
{
 unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
 unsigned long temp0,temp1,temp2,temp3;
 long tempm,tempn,fnLmL;
 tempn = (long)R[n];
 tempm = (long)R[m];
 if (tempn<0) tempn = 0 - tempn;
 if (tempm<0) tempm = 0 - tempm;
 if ((long)(R[n]^R[m])<0) fnLmL = -1;
 else fnLmL = 0;
 temp1 = (unsigned long)tempn;
 temp2 = (unsigned long)tempm;
 RnL = temp1&0x0000FFFF;
 RnH = (temp1>>16)&0x0000FFFF;
 RmL = temp2&0x0000FFFF;
 RmH = (temp2>>16)&0x0000FFFF;
Rev. 1.50, 10/04, page 326 of 610
 temp0 = RmL*RnL;
 temp1 = RmH*RnL;
 temp2 = RmL*RnH;
 temp3 = RmH*RnH;
 Res2 = 0;
 Res1 = temp1+temp2;
 if (Res1<temp1) Res2 += 0x00010000;
 temp1 = (Res1<<16)&0xFFFF0000;
 Res0 = temp0 + temp1;
 if (Res0<temp0) Res2++;
 Res2 = Res2 + ((Res1>>16)&0x0000FFFF) + temp3;
 if (fnLmL<0) {
 Res2 = ~
Res2;
 if (Res0==0)
 Res2++;
 else
 Res0 = (~
Res0) + 1;
 }
 MACH = Res2;
 MACL = Res0;
 PC +=2;
 }
Example:
DMULS.L R0,R1 ;Before execution R0 = H'FFFFFFFE, R1 = H'00005555
 ;After execution MACH = H'FFFFFFFF, MACL = H'FFFF5556
STS MACH,R0 ;Get operation result (upper)
STS MACL,R1 ;Get operation result (lower)
Rev. 1.50, 10/04, page 327 of 610
11.1.19 DMULU.L (Double-length Multiply as Unsigned): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DMULU.L Rm,Rn Unsigned,
Rn × Rm →MAC
0011nnnnmmmm0101 2 —
Description: This instruction performs 32-bit multiplication of the contents of general register Rn
by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The
multiplication is performed as an unsigned arithmetic operation.
Notes: None
Operation:
DMULU(long m, long n) /* DMULU.L Rm,Rn */
{
 unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
 unsigned long temp0,temp1,temp2,temp3;
 RnL = R[n] & 0x0000FFFF;
 RnH = (R[n]>>16) & 0x0000FFFF;
 RmL = R[m] & 0x0000FFFF;
 RmH = (R[m]>>16) & 0x0000FFFF;
 temp0 = RmL*RnL;
 temp1 = RmH*RnL;
 temp2 = RmL*RnH;
 temp3 = RmH*RnH;
 Res2 = 0;
 Res1 = temp1 + temp2;
 if (Res1<temp1) Res2 += 0x00010000;
 temp1 = (Res1<<16) & 0xFFFF0000;
 Res0 = temp0 + temp1;
Rev. 1.50, 10/04, page 328 of 610
 if (Res0<temp0) Res2++;
 Res2 = Res2 + ((Res1>>16)&0x0000FFFF) + temp3;
 MACH = Res2;
 MACL = Res0;
 PC += 2;
}
Example:
DMULU.L R0,R1 ;Before execution R0 = H'FFFFFFFE, R1 = H'00005555
 ;After execution MACH = H'00005554, MACL = H'FFFF5556
STS MACH,R0 ;Get operation result (upper)
STS MACL,R1 ;Get operation result (lower)
Rev. 1.50, 10/04, page 329 of 610
11.1.20 DT (Decrement and Test): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DT Rn Rn – 1 → Rn;
if Rn = 0, 1 → T
if Rn ≠ 0, 0 → T
0100nnnn00010000 1 Result of
comparison
Description: This instruction decrements the contents of general register Rn by 1 and compares
the result with zero. If the result is zero, the T bit is set to 1. If the result is nonzero, the T bit is
cleared to 0.
Notes: None
Operation:
DT(long n)/* DT Rn */
{
 R[n]--;
 if (R[n]==0) T = 1;
 else T = 0;
 PC += 2;
}
Example:
 MOV #4,R5 ;Set loop count
LOOP:
 ADD R0,R1 ;
 DT R5 ;Decrement R5 value and check for 0.
 BF LOOP ;If T = 0, branch to LOOP (in this example, 4 loops are executed).
Rev. 1.50, 10/04, page 330 of 610
11.1.21 EXTS (Extend as Signed): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
EXTS.B Rm,Rn Rm sign-extended from
byte → Rn
0110nnnnmmmm1110 1 —
EXTS.W Rm,Rn Rm sign-extended from
word → Rn
0110nnnnmmmm1111 1 —
Description:
This instruction sign-extends the contents of general register Rm and stores the result in Rn.
For a byte specification, the value of Rm bit 7 is transferred to Rn bits 8 to 31. For a word
specification, the value of Rm bit 15 is transferred to Rn bits 16 to 31.
Notes: None
Operation:
EXTSB(long m, long n) /* EXTS.B Rm,Rn */
{
 R[n] = R[m];
 if ((R[m] & 0x00000080)==0) R[n] &=0x000000FF;
 else R[n] |= 0xFFFFFF00;
 PC += 2;
}
EXTSW(long m, long n) /* EXTS.W Rm,Rn */
{
 R[n] = R[m];
 if ((R[m] & 0x00008000)==0) R[n] &=0x0000FFFF;
 else R[n] |= 0xFFFF0000;
 PC += 2;
}
Rev. 1.50, 10/04, page 331 of 610
Example:
EXTS.B R0,R1 ;Before execution R0 = H'00000080
 ;After execution R1 = H'FFFFFF80
EXTS.W R0,R1 ;Before execution R0 = H'00008000
 ;After execution R1 = H'FFFF8000
Rev. 1.50, 10/04, page 332 of 610
11.1.22 EXTU (Extend as Unsigned): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
EXTU.B Rm,Rn Rm zero-extended from
byte → Rn
0110nnnnmmmm1100 1 —
EXTU.W Rm,Rn Rm zero-extended from
word → Rn
0110nnnnmmmm1101 1 —
Description: This instruction zero-extends the contents of general register Rm and stores the
result in Rn.
For a byte specification, 0 is transferred to Rn bits 8 to 31. For a word specification, 0 is
transferred to Rn bits 16 to 31.
Notes: None
Operation:
EXTUB(long m, long n) /* EXTU.B Rm,Rn */
{
 R[n] = R[m];
 R[n] &= 0x000000FF;
 PC += 2;
}
EXTUW(long m, long n) /* EXTU.W Rm,Rn */
{
 R[n] = R[m];
 R[n] &= 0x0000FFFF;
 PC += 2;
}
Example:
EXTU.B R0,R1 ;Before execution R0 = H'FFFFFF80
 ;After execution R1 = H'00000080
EXTU.W R0,R1 ;Before execution R0 = H'FFFF8000
 ;After execution R1 = H'00008000
Rev. 1.50, 10/04, page 333 of 610
11.1.23 ICBI (Instruction Cache Block Invalidate): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
ICBI @Rn Invalidates the instruction
cache block indicated by
logical address Rn
0000nnnn11100011 13 —
Description: This instruction accesses the instruction cache at the effective address indicated by
the contents of Rn. When the cache is hit, the corresponding cache block is invalidated (the V bit
is cleared to 0). At this time, write-back is not performed. No operation is performed in the case of
a cache miss or access to a non-cache area.
Notes: None
Operation:
ICBI(int n) /* ICBI @Rn */
{
 invalidate_instruction_cache_block(R[n]);
 PC += 2;
}
Example: When a program is overwriting RAM to modify its own execution, the corresponding
block of the instruction cache should be invalidated by the ICBI instruction. This prevents
execution of the program from the instruction cache, where the non-overwritten instructions are
stored.
Possible Exceptions: Exceptions may occur when invalidation is not performed.
• Instruction TLB multiple-hit exception
• Instruction TLB miss exception
• Instruction TLB protection violation exception
• Instruction address error
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 334 of 610
11.1.24 JMP (Jump): Branch Instruction
Format Operation Instruction Code Cycle T Bit
JMP @Rn Rn → PC 0100nnnn00101011 1 —
Description: Unconditionally makes a delayed branch to the address specified by Rn.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
JMP(int n)/* JMP @Rn */
{
 unsigned int temp;
 temp = PC;
 PC = R[n];
 Delay_Slot(temp+2);
}
Example:
 MOV.L JMP_TABLE,R0 ;R0 = TRGET address
 JMP @R0 ;Branch to TRGET.
 MOV R0,R1 ;MOV executed before branch.
 .align 4
JMP_TABLE: .data.l TRGET ;Jump table
 ...........
TRGET: ADD #1,R1 ;← Branch destination
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 335 of 610
11.1.25 LDC (Load to Control Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDC Rm, GBR Rm → GBR 0100mmmm00011110 1 —
LDC Rm, VBR Rm → VBR 0100mmmm00101110 1 —
LDC Rm, SGR Rm → SGR 0100mmmm00111010 4 —
LDC Rm, SSR Rm → SSR 0100mmmm00111110 1 —
LDC Rm, SPC Rm → SPC 0100mmmm01001110 1
LDC Rm, DBR Rm → DBR 0100mmmm11111010 4 —
LDC Rm, R0_BANK Rm → R0_BANK 0100mmmm10001110 1 —
LDC Rm, R1_BANK Rm → R1_BANK 0100mmmm10011110 1 —
LDC Rm, R2_BANK Rm → R2_BANK 0100mmmm10101110 1 —
LDC Rm, R3_BANK Rm → R3_BANK 0100mmmm10111110 1 —
LDC Rm, R4_BANK Rm → R4_BANK 0100mmmm11001110 1 —
LDC Rm, R5_BANK Rm → R5_BANK 0100mmmm11011110 1 —
LDC Rm, R6_BANK Rm → R6_BANK 0100mmmm11101110 1 —
LDC Rm, R7_BANK Rm → R7_BANK 0100mmmm11111110 1 —
LDC.L @Rm+, GBR (Rm) → GBR, Rm+4 → Rm 0100mmmm00010111 1 —
LDC.L @Rm+, VBR (Rm) → VBR, Rm+4 → Rm 0100mmmm00100111 1 —
LDC.L @Rm+, SGR (Rm) → SGR, Rm+4 → Rm 0100mmmm00110110 4 —
LDC.L @Rm+, SSR (Rm) → SSR, Rm+4 → Rm 0100mmmm00110111 1 —
LDC.L @Rm+, SPC (Rm) → SPC, Rm+4 → Rm 0100mmmm01000111 1 —
LDC.L @Rm+, DBR (Rm) → DBR, Rm+4 → Rm 0100mmmm11110110 4 —
LDC.L @Rm+, R0_BANK (Rm) → R0_BANK, Rm+4 → Rm 0100mmmm10000111 1 —
LDC.L @Rm+, R1_BANK (Rm) → R1_BANK, Rm+4 → Rm 0100mmmm10010111 1 —
LDC.L @Rm+, R2_BANK (Rm) → R2_BANK, Rm+4 → Rm 0100mmmm10100111 1 —
LDC.L @Rm+, R3_BANK (Rm) → R3_BANK, Rm+4 → Rm 0100mmmm10110111 1 —
LDC.L @Rm+, R4_BANK (Rm) → R4_BANK, Rm+4 → Rm 0100mmmm11000111 1 —
LDC.L @Rm+, R5_BANK (Rm) → R5_BANK, Rm+4 → Rm 0100mmmm11010111 1 —
LDC.L @Rm+, R6_BANK (Rm) → R6_BANK, Rm+4 → Rm 0100mmmm11100111 1 —
LDC.L @Rm+, R7_BANK (Rm) → R7_BANK, Rm+4 → Rm 0100mmmm11110111 1 —
Description: These instructions store the source operand in the control register GBR, VBR, SSR,
SPC, DBR, SGR, or R0_BANK to R7_BANK.
Rev. 1.50, 10/04, page 336 of 610
Notes: With the exception of LDC Rm,GBR and LDC.L @Rm+,GBR, the LDC/LDC.L
instructions are privileged instructions and can only be used in privileged mode. Use in user mode
will cause an illegal instruction exception. However, LDC Rm,GBR and LDC.L @Rm+,GBR can
also be used in user mode.
With the LDC Rm, Rn_BANK and LDC.L @Rm, Rn_BANK instructions, Rn_BANK0 is
accessed when the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.
Operation:
 LDCGBR(int m) /* LDC Rm,GBR */
 {
 GBR = R[m];
 PC += 2;
 }
 LDCVBR(int m) /* LDC Rm,VBR : Privileged */
 {
 VBR = R[m];
 PC += 2;
 }
 LDCSGR(int m) /* LDC Rm,SGR : Privileged */
 {
 SGR = R[m];
 PC += 2;
 }
 LDCSSR(int m) /* LDC Rm,SSR : Privileged */
 {
 SSR = R[m],
 PC += 2;
 }
Rev. 1.50, 10/04, page 337 of 610
 LDCSPC(int m) /* LDC Rm,SPC : Privileged */
 {
 SPC = R[m];
 PC += 2;
 }
 LDCDBR(int m) /* LDC Rm,DBR : Privileged */
 {
 DBR = R[m];
 PC += 2;
 }
 LDCRn_BANK(int m) /* LDC Rm,Rn_BANK : Privileged */
 /* n=0–7 */
 {
 Rn_BANK = R[m];
 PC += 2;
 }
 LDCMGBR(int m) /* LDC.L @Rm+,GBR */
 {
 GBR=Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
 LDCMVBR(int m) /* LDC.L @Rm+,VBR : Privileged */
 {
 VBR = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
Rev. 1.50, 10/04, page 338 of 610
 LDCMSGR(int m) /* LDC.L @Rm+,SGR : Privileged */
 {
 SGR = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
 LDCMSSR(int m) /* LDC.L @Rm+,SSR : Privileged */
 {
 SSR=Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
 LDCMSPC(int m) /* LDC.L @Rm+,SPC : Privileged */
 {
 SPC = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
 LDCMDBR(int m) /* LDC.L @Rm+,DBR : Privileged */
 {
 DBR = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
 LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */
 /* n=0–7 */
 {
 Rn_BANK = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
 }
Rev. 1.50, 10/04, page 339 of 610
Possible Exceptions:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 340 of 610
11.1.26 LDS (Load to System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDS Rm,MACH Rm → MACH 0100mmmm00001010 1 —
LDS Rm,MACL Rm → MACL 0100mmmm00011010 1 —
LDS Rm,PR Rm→ PR 0100mmmm00101010 1 —
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 1 —
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 1 —
LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1 —
Description: Stores the source operand into the system registers MACH, MACL, or PR.
Notes: None
Operation:
LDSMACH(long m) /* LDS Rm,MACH */
{
 MACH = R[m];
 PC += 2;
}
LDSMACL(long m) /* LDS Rm,MACL */
{
 MACL = R[m];
 PC += 2;
}
LDSPR(long m) /* LDS Rm,PR */
{
 PR = R[m];
 PC += 2;
}
Rev. 1.50, 10/04, page 341 of 610
LDSMMACH(long m) /* LDS.L @Rm+,MACH */
{
 MACH = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
}
LDSMMACL(long m) /* LDS.L @Rm+,MACL */
{
 MACL = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
}
LDSMPR(long m) /* LDS.L @Rm+,PR */
{
 PR = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
}
Example:
LDS R0,PR ; Before execution R0 = H'12345678, PR = H'00000000
 ; After execution PR = H'12345678
LDS.L @R15+,MACL ; Before execution R15 = H'10000000
 ; After execution R15 = H'10000004, MACL = (H'10000000)
Possible Exceptions: Exception may occur when LDS.L instruction is executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 342 of 610
11.1.27 LDTLB (Load PTEH/PTEL to TLB): System Control Instruction (Privileged
Instruction)
Format Operation Instruction Code Cycle T Bit
LDTLB PTEH/PTEL → TLB 0000000000111000 1 —
Description: This instruction loads the contents of the PTEH/PTEL registers into the TLB
(translation lookaside buffer) specified by MMUCR.URC (random counter field in the MMC
control register).
LDTLB is a privileged instruction, and can only be used in privileged mode. Use of this
instruction in user mode will cause an illegal instruction exception.
Notes: As this instruction loads the contents of the PTEH/PTEL registers into a TLB, it should be
used either with the MMU disabled, or in the P1 or P2 virtual space with the MMU enabled (see
section 7, Memory Management Unit (MMU), for details). After this instruction is issued, there
must be at least one instruction between the LDTLB instruction and issuance of an instruction
relating to address to the P0, U0, and P3 areas (i.e. BRAF, BSRF, JMP, JSR, RTS, or RTE).
Operation:
LDTLB( ) /*LDTLB */
{
 TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;
 TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;
 TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;
 TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 |
 (PTEL & 0x00000010) >> 4;
 TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;
 TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;
 TLB[MMUCR.URC].WT = (PTEH & 0x00000001);
 TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;
 TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;
 TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;
 PC += 2;
}
Rev. 1.50, 10/04, page 343 of 610
Example:
MOV @R0,R1 ;Load page table entry (upper) into R1
MOV R1,@R2 ;Load R1 into PTEH; R2 is PTEH address (H'FF000000)
LDTLB ;Load PTEH, PTEL registers into TLB
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 344 of 610
11.1.28 MAC.L (Multiply and Accumulate Long): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MAC.L @Rm+,@Rn+ Signed,
(Rn) × (Rm) + MAC → MAC
Rn + 4 → Rn, Rm + 4 → Rm
0000nnnnmmmm1111 5 —
Description: This instruction performs signed multiplication of the 32-bit operands whose
addresses are the contents of general registers Rm and Rn, adds the 64-bit result to the MAC
register contents, and stores the result in the MAC register. Operands Rm and Rn are each
incremented by 4 each time they are read.
If the S bit is 0, the 64-bit result is stored in the linked MACH and MACL registers.
If the S bit is 1, the addition to the MAC register contents is a saturation operation at the 48th bit
from the LSB. In a saturation operation, only the lower 48 bits of the MAC register are valid, and
the result range is limited to H'FFFF800000000000 (minimum value) to H'00007FFFFFFFFFFF
(maximum value).
Notes: None
Operation:
MACL(long m, long n) /* MAC.L @Rm+,@Rn+ */
{
 unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
 unsigned long temp0,temp1,temp2,temp3;
 long tempm,tempn,fnLmL;
 tempn = (long)Read_Long(R[n]);
 R[n] += 4;
 tempm = (long)Read_Long(R[m]);
 R[m] += 4;
 if ((long)(tempn^tempm)<0) fnLmL = -1;
 else fnLmL = 0;
 if (tempn<0) tempn = 0-tempn;
 if (tempm<0) tempm = 0-tempm;
Rev. 1.50, 10/04, page 345 of 610
 temp1 = (unsigned long)tempn;
 temp2 = (unsigned long)tempm;
 RnL = temp1&0x0000FFFF;
 RnH = (temp1>>16) & 0x0000FFFF;
 RmL = temp2 & 0x0000FFFF;
 RmH = (temp2>>16) & 0x0000FFFF;
 temp0 = RmL*RnL;
 temp1 = RmH*RnL;
 temp2 = RmL*RnH;
 temp3 = RmH*RnH;
 Res2 = 0;
Res1 = temp1 + temp2;
if (Res1<temp1) Res2 += 0x00010000;
temp1 =(Res1<<16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0<temp0) Res2++;
Res2 = Res2 + ((Res1>>16) & 0x0000FFFF) + temp3;
if(fnLmL<0){
 Res2 = ~
Res2;
 if (Res0==0) Res2++;
 else Res0 = (~
Res0)+1;
}
if(S==1){
 Res0 = MACL + Res0;
 if (MACL>Res0) Res2++;
 if (MACH & 0x00008000);
 else Res2 += MACH|0xFFFF0000;
 Res2 += MACH&0x00007FFF;
Rev. 1.50, 10/04, page 346 of 610
 if(((long)Res2<0)&&(Res2 < 0xFFFF8000)){
 Res2 = 0xFFFF8000;
 Res0 = 0x00000000;
 }
 if(((long)Res2>0)&&(Res2 > 0x00007FFF)){
 Res2 = 0x00007FFF;
 Res0 = 0xFFFFFFFF;
 };
 MACH = (Res2 & 0x0000FFFF)|(MACH & 0xFFFF0000);
 MACL = Res0;
}
 else {
 Res0 = MACL + Res0;
 if (MACL>Res0) Res2++;
 Res2 += MACH;
 MACH = Res2;
 MACL = Res0;
 }
 PC += 2;
}
Rev. 1.50, 10/04, page 347 of 610
Example:
 MOVA TBLM,R0 ;Get table address
 MOV R0,R1;
 MOVA TBLN,R0 ;Get table address
 CLRMAC ;MAC register initialization
 MAC.L @R0+,@R1+ ;
 MAC.L @R0+,@R1+ ;
 STS MACL,R0 ;Get result in R0
 .........
 .align 2 ;
TBLM .data.l H'1234ABCD ;
 .data.l H'5678EF01 ;
TBLN .data.l H'0123ABCD ;
 .data.l H'4567DEF0 ;
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 348 of 610
11.1.29 MAC.W (Multiply and Accumulate Word): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MAC.W @Rm+,@Rn+
MAC @Rm+,@Rn+
Signed,
(Rn) × (Rm) + MAC →MAC
Rn + 2 → Rn, Rm + 2 → Rm
0100nnnnmmmm1111 4 —
Description: This instruction performs signed multiplication of the 16-bit operands whose
addresses are the contents of general registers Rm and Rn, adds the 32-bit result to the MAC
register contents, and stores the result in the MAC register. Operands Rm and Rn are each
incremented by 2 each time they are read.
If the S bit is 0, a 16 × 16 + 64 → 64-bit multiply-and-accumulate operation is performed, and the
64-bit result is stored in the linked MACH and MACL registers.
If the S bit is 1, a 16 × 16 + 32 → 32-bit multiply-and-accumulate operation is performed, and the
addition to the MAC register contents is a saturation operation. In a saturation operation, only the
MACL register is valid, and the result range is limited to H'80000000 (minimum value) to
H'7FFFFFFF (maximum value). If overflow occurs, the LSB of the MACH register is set to 1.
H'80000000 (minimum value) is stored in the MACL register if the result overflows in the
negative direction, and H'7FFFFFFF (maximum value) is stored if the result overflows in the
positive direction
Notes: If the S bit is 0, a 16 × 16 + 64 → 64-bit multiply-and-accumulate operation is performed.
Rev. 1.50, 10/04, page 349 of 610
Operation:
MACW(long m, long n) /* MAC.W @Rm+,@Rn+ */
{
 long tempm,tempn,dest,src,ans;
 unsigned long templ;
 tempn = (long)Read_Word(R[n]);
 R[n] += 2;
 tempm = (long)Read_Word(R[m]);
 R[m] += 2;
 templ = MACL;
 tempm = ((long)(short)tempn*(long)(short)tempm);
 if ((long)MACL>=0) dest = 0;
 else dest = 1;
 if ((long)tempm>=0) {
 src = 0;
 tempn = 0;
 }
 else {
 src = 1;
 tempn = 0xFFFFFFFF;
 }
 src += dest;
 MACL += tempm;
 if ((long)MACL>=0) ans = 0;
 else ans = 1;
 ans += dest;
 if (S==1) {
 if (ans==1) {
 if (src==0) MACL = 0x7FFFFFFF;
 if (src==2) MACL = 0x80000000;
 }
 }
Rev. 1.50, 10/04, page 350 of 610
 else {
 MACH += tempn;
 if (templ>MACL) MACH += 1;
 }
 PC += 2;
}
Example:
 MOVA TBLM,R0 ;Get table address
 MOV R0,R1 ;
 MOVA TBLN,R0 ;Get table address
 CLRMAC ;MAC register initialization
 MAC.W @R0+,@R1+ ;
 MAC.W @R0+,@R1+ ;
 STS MACL,R0 ;Get result in R0
 ...........
 .align 2 ;
TBLM .data.w H'1234 ;
 .data.w H'5678 ;
TBLN .data.w H'0123 ;
 .data.w H'4567 ;
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 351 of 610
11.1.30 MOV (Move data): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 1 —
MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 1 —
MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 1 —
MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 1 —
MOV.B @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0000 1 —
MOV.W @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0001 1 —
MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 1 —
MOV.B Rm,@-Rn Rn-1 → Rn, Rm → (Rn ) 0010nnnnmmmm0100 1 —
MOV.W Rm,@-Rn Rn-2 → Rn, Rm → (Rn ) 0010nnnnmmmm0101 1 —
MOV.L Rm,@-Rn Rn-4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1 —
MOV.B @Rm+,Rn (Rm) → sign extension → Rn,
Rm + 1 → Rm
0110nnnnmmmm0100 1 —
MOV.W @Rm+,Rn (Rm) → sign extension → Rn,
Rm + 2 → Rm
0110nnnnmmmm0101 1 —
MOV.L @Rm+,Rn (Rm) → Rn, Rm + 4 → Rm 0110nnnnmmmm0110 1 —
MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 1 —
MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 1 —
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 1 —
MOV.B @(R0,Rm),Rn (R0 + Rm) → sign extension → Rn 0000nnnnmmmm1100 1 —
MOV.W @(R0,Rm),Rn (R0 + Rm) → sign extension → Rn 0000nnnnmmmm1101 1 —
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 1 —
Description: This instruction transfers the source operand to the destination. When an operand is
memory, the data size can be specified as byte, word, or longword. When the source operand is
memory, the loaded data is sign-extended to longword before being stored in the register.
Notes: None
Rev. 1.50, 10/04, page 352 of 610
Operation:
MOV(long m, long n) /* MOV Rm,Rn */
{
 R[n] = R[m];
 PC += 2;
}
MOVBS(long m, long n) /* MOV.B Rm,@Rn */
{
 Write_Byte(R[n],R[m]);
 PC += 2;
}
MOVWS(long m, long n) /* MOV.W Rm,@Rn */
{
 Write_Word(R[n],R[m]);
 PC += 2;
}
MOVLS(long m, long n) /* MOV.L Rm,@Rn */
{
 Write_Long(R[n],R[m]);
 PC += 2;
}
MOVBL(long m, long n) /* MOV.B @Rm,Rn */
{
 R[n] = (long)Read_Byte(R[m]);
 if ((R[n]&0x80)==0) R[n] &= 0x000000FF;
 else R[n] |= 0xFFFFFF00;
 PC += 2;
}
Rev. 1.50, 10/04, page 353 of 610
MOVWL(long m, long n) /* MOV.W @Rm,Rn */
{
 R[n] = (long)Read_Word(R[m]);
 if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;
 else R[n] |= 0xFFFF0000;
 PC += 2;
}
MOVLL(long m, long n) /* MOV.L @Rm,Rn */
{
 R[n] = Read_Long(R[m]);
 PC += 2;
}
MOVBM(long m, long n) /* MOV.B Rm,@-Rn */
{
 Write_Byte(R[n]-1,R[m]);
 R[n] -= 1;
 PC += 2;
}
MOVWM(long m, long n) /* MOV.W Rm,@-Rn */
{
 Write_Word(R[n]-2,R[m]);
 R[n] -= 2;
 PC += 2;
}
MOVLM(long m, long n) /* MOV.L Rm,@-Rn */
{
 Write_Long(R[n]-4,R[m]);
 R[n] -= 4;
 PC += 2;
}
Rev. 1.50, 10/04, page 354 of 610
MOVBP(long m, long n) /* MOV.B @Rm+,Rn */
{
 R[n] = (long)Read_Byte(R[m]);
 if ((R[n]&0x80)==0) R[n] &= 0x000000FF;
 else R[n] |= 0xFFFFFF00;
 if (n!=m) R[m] += 1;
 PC += 2;
}
MOVWP(long m, long n) /* MOV.W @Rm+,Rn */
{
 R[n] = (long)Read_Word(R[m]);
 if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;
 else R[n] |= 0xFFFF0000;
 if (n!=m) R[m] += 2;
 PC += 2;
}
MOVLP(long m, long n) /* MOV.L @Rm+,Rn */
{
 R[n] = Read_Long(R[m]);
 if (n!=m) R[m] += 4;
 PC += 2;
}
MOVBS0(long m, long n) /* MOV.B Rm,@(R0,Rn) */
{
 Write_Byte(R[n]+R[0],R[m]);
 PC += 2;
}
MOVWS0(long m, long n) /* MOV.W Rm,@(R0,Rn) */
{
 Write_Word(R[n]+R[0],R[m]);
 PC+=2;
}
Rev. 1.50, 10/04, page 355 of 610
MOVLS0(long m, long n) /* MOV.L Rm,@(R0,Rn) */
{
 Write_Long(R[n]+R[0],R[m]);
 PC += 2;
}
MOVBL0(long m, long n) /* MOV.B @(R0,Rm),Rn */
{
 R[n] = (long)Read_Byte(R[m]+R[0]);
 if ((R[n]&0x80)==0) R[n] &= 0x000000FF;
 else R[n] |= 0xFFFFFF00;
 PC += 2;
}
MOVWL0(long m, long n) /* MOV.W @(R0,Rm),Rn */
{
 R[n] = (long)Read_Word(R[m]+R[0]);
 if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;
 else R[n] |= 0xFFFF0000;
 PC += 2;
}
MOVLL0(long m, long n) /* MOV.L @(R0,Rm),Rn */
{
 R[n] = Read_Long(R[m]+R[0]);
 PC += 2;
}
Rev. 1.50, 10/04, page 356 of 610
Example:
MOV R0,R1 ;Before execution R0 = H'FFFFFFFF, R1 = H'00000000
 ;After execution R1 = H'FFFFFFFF
MOV.W R0,@R1 ;Before execution R0 = H'FFFF7F80
 ;After execution (R1) = H'7F80
MOV.B @R0,R1 ;Before execution (R0) = H'80, R1 = H'00000000
 ;After execution R1 = H'FFFFFF80
MOV.W R0,@-R1 ;Before execution R0 = H'AAAAAAAA, (R1) = H'FFFF7F80
 ;After execution R1 = H'FFFF7F7E, (R1) = H'AAAA
MOV.L @R0+,R1 ;Before execution R0 = H'12345670
 ;After execution R0 = H'12345674, R1 = (H'12345670)
MOV.B R1,@(R0,R2) ;Before execution R2 = H'00000004, R0 = H'10000000
 ;After execution R1 = (H'10000004)
MOV.W @(R0,R2),R1 ;Before execution R2 = H'00000004, R0 = H'10000000
 ;After execution R1 = (H'10000004)
Possible Exceptions: Exceptions may occur when MOV instructions without MOV Rm, Rn are
executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
• Initial page write exception (only write operation)
Rev. 1.50, 10/04, page 357 of 610
11.1.31 MOV (Move Constant Value): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOV #imm,Rn imm → sign extension → Rn 1110nnnniiiiiiii 1 —
MOV.W @(disp*,PC),Rn (disp × 2 + PC + 4) → sign
extension → Rn
1001nnnndddddddd 1 —
MOV.L @(disp*,PC),Rn (disp × 4 + PC &
H'FFFFFFFC + 4) → Rn
1101nnnndddddddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Description: This instruction stores immediate data, sign-extended to longword, in general
register Rn. In the case of word or longword data, the data is stored from memory address (PC + 4
+ displacement × 2) or (PC + 4 + displacement × 4).
With word data, the 8-bit displacement is multiplied by two after zero-extension, and so the
relative distance from the table is in the range up to PC + 4 + 510 bytes. The PC value is the
address of this instruction.
With longword data, the 8-bit displacement is multiplied by four after zero-extension, and so the
relative distance from the operand is in the range up to PC + 4 + 1020 bytes. The PC value is the
address of this instruction. A value with the lower 2 bits adjusted to B'00 is used in address
calculation.
Notes: If a PC-relative load instruction is executed in a delay slot, a slot illegal instruction
exception will be generated.
Rev. 1.50, 10/04, page 358 of 610
Operation:
MOVI(int i, int n) /* MOV #imm,Rn */
{
 if ((i&0x80)==0) R[n] = (0x000000FF & i);
 else R[n] = (0xFFFFFF00 | i);
 PC += 2;
}
MOVWI(int d, int n) /* MOV.W @(disp,PC),Rn */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[n] = (int)Read_Word(PC+4+(disp<<1));
 if ((R[n]&0x8000)==0) R[n] &= 0x0000FFFF;
 else R[n] |= 0xFFFF0000;
 PC += 2;
}
 MOVLI(int d, int n)/* MOV.L @(disp,PC),Rn */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & (int)d);
 R[n] = Read_Long((PC & 0xFFFFFFFC)+4+(disp<<2));
 PC += 2;
}
Rev. 1.50, 10/04, page 359 of 610
Example:
Address
1000 MOV #H'80,R1 ;R1 = H'FFFFFF80
1002 MOV.W IMM,R2 ;R2 = H'FFFF9ABC IMM means (PC + 4 + H'08)
1004 ADD #-1,R0 ;
1006 TST R0,R0 ;
1008 MOV.L @(3*,PC),R3 ;R3 = H'12345678
100A BRA NEXT ;Delayed branch instruction
100C NOP
100E IMM .data.w H'9ABC ;
1010 .data.w H'1234 ;
1012 NEXT JMP @R3 ;Distination of BRA branch instruction
1014 CMP/EQ#0,R0 ;
 .align 4;
1018 .data.l H'12345678 ;
101C .data.l H'9ABCDEF0 ;
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Possible Exceptions: Exceptions may occur when PC-relative load instruction is executed.
• Data TLB multiple-hit exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 360 of 610
11.1.32 MOV (Move Global Data): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOV.B @(disp*,GBR),R0 (disp + GBR) → sign
extension → R0
11000100dddddddd 1 —
MOV.W @(disp*,GBR),R0 (disp × 2 + GBR) →
sign extension → R0
11000101dddddddd 1 —
MOV.L @(disp*,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1 —
MOV.B R0,@(disp*,GBR) R0 → (disp + GBR) 11000000dddddddd 1 —
MOV.W R0,@(disp*,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1 —
MOV.L R0,@(disp*,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Description: This instruction transfers the source operand to the destination. Byte, word, or
longword can be specified as the data size, but the register is always R0. If the transfer data is
byte-size, the 8-bit displacement is only zero-extended, so a range up to +255 bytes can be
specified. If the transfer data is word-size, the 8-bit displacement is multiplied by two after zeroextension, enabling a range up to +510 bytes to be specified. With longword transfer data, the 8-
bit displacement is multiplied by four after zero-extension, enabling a range up to +1020 bytes to
be specified.
When the source operand is memory, the loaded data is sign-extended to longword before being
stored in the register.
Notes: When loading, the destination register is always R0.
Rev. 1.50, 10/04, page 361 of 610
Operation:
MOVBLG(int d) /* MOV.B @(disp,GBR),R0 */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[0] = (int)Read_Byte(GBR+disp);
 if ((R[0]&0x80)==0) R[0] &= 0x000000FF;
 else R[0] |= 0xFFFFFF00;
 PC += 2;
}
MOVWLG(int d) /* MOV.W @(disp,GBR),R0 */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[0] = (int)Read_Word(GBR+(disp<<1));
 if ((R[0]&0x8000)==0) R[0] &= 0x0000FFFF;
 else R[0] |= 0xFFFF0000;
 PC += 2;
}
MOVLLG(int d) /* MOV.L @(disp,GBR),R0 */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[0] = Read_Long(GBR+(disp<<2));
 PC += 2;
}
Rev. 1.50, 10/04, page 362 of 610
MOVBSG(int d) /* MOV.B R0,@(disp,GBR) */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 Write_Byte(GBR+disp,R[0]);
 PC += 2;
}
MOVWSG(int d) /* MOV.W R0,@(disp,GBR) */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 Write_Word(GBR+(disp<<1),R[0]);
 PC += 2;
}
MOVLSG(int d) /* MOV.L R0,@(disp,GBR) */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & (long)d);
 Write_Long(GBR+(disp<<2),R[0]);
 PC += 2;
}
Example:
MOV.L @(2*,GBR),R0 ;Before execution (GBR+8) = H'12345670
 ;After execution R0 = H'12345670
MOV.B R0,@(1*,GBR) ;Before execution R0 = H'FFFF7F80
 ;After execution (GBR+1) = H'80
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Rev. 1.50, 10/04, page 363 of 610
Possible Exceptions:
• Data TLB multiple-hit exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
• Initial page write exception (only write operation)
Rev. 1.50, 10/04, page 364 of 610
11.1.33 MOV (Move Structure Data): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOV.B R0,@(disp*,Rn) R0 → (disp + Rn) 10000000nnnndddd 1 —
MOV.W R0,@(disp*,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd 1 —
MOV.L Rm,@(disp*,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1 —
MOV.B @(disp*,Rm),R0 (disp + Rm) → sign
extension → R0
10000100mmmmdddd 1 —
MOV.W @(disp*,Rm),R0 (disp × 2 + Rm) → sign
extension → R0
10000101mmmmdddd 1 —
MOV.L @(disp*,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Description: This instruction transfers the source operand to the destination. It is ideal for
accessing data inside a structure or stack. Byte, word, or longword can be specified as the data
size, but with byte or word data the register is always R0.
If the data is byte-size, the 4-bit displacement is only zero-extended, so a range up to +15 bytes
can be specified. If the data is word-size, the 4-bit displacement is multiplied by two after zeroextension, enabling a range up to +30 bytes to be specified. With longword data, the 4-bit
displacement is multiplied by four after zero-extension, enabling a range up to +60 bytes to be
specified. If a memory operand cannot be reached, the previously described @(R0,Rn) mode must
be used.
When the source operand is memory, the loaded data is sign-extended to longword before being
stored in the register.
Notes: When loading byte or word data, the destination register is always R0. Therefore, if the
following instruction attempts to reference R0, it is kept waiting until completion of the load
instruction. This allows optimization by changing the order of instructions.
MOV.B
AND
ADD
@(2,R1),R0
#80,R0
#20,R1
MOV.B
ADD
AND
@(2,R1),R0
#20,R1
#80,R0
Rev. 1.50, 10/04, page 365 of 610
Operation:
MOVBS4(long d, long n) /* MOV.B R0,@(disp,Rn) */
{
 long disp;
 disp = (0x0000000F & (long)d);
 Write_Byte(R[n]+disp,R[0]);
 PC += 2;
}
MOVWS4(long d, long n) /* MOV.W R0,@(disp,Rn) */
{
 long disp;
 disp = (0x0000000F & (long)d);
 Write_Word(R[n]+(disp<<1),R[0]);
 PC += 2;
}
MOVLS4(long m, long d, long n) /* MOV.L Rm,@(disp,Rn) */
{
 long disp;
 disp = (0x0000000F & (long)d);
 Write_Long(R[n]+(disp<<2),R[m]);
 PC += 2;
}
MOVBL4(long m, long d) /* MOV.B @(disp,Rm),R0 */
{
 long disp;
 disp = (0x0000000F & (long)d);
 R[0] = Read_Byte(R[m]+disp);
 if ((R[0]&0x80)==0) R[0] &= 0x000000FF;
 else R[0] |= 0xFFFFFF00;
 PC += 2;
}
Rev. 1.50, 10/04, page 366 of 610
MOVWL4(long m, long d) /* MOV.W @(disp,Rm),R0 */
{
 long disp;
 disp = (0x0000000F & (long)d);
 R[0] = Read_Word(R[m]+(disp<<1));
 if ((R[0]&0x8000)==0) R[0] &= 0x0000FFFF;
 else R[0] |= 0xFFFF0000;
 PC += 2;
}
MOVLL4(long m, long d, long n) /* MOV.L @(disp,Rm),Rn */
{
 long disp;
 disp = (0x0000000F & (long)d);
 R[n] = Read_Long(R[m]+(disp<<2));
 PC += 2;
}
Example:
MOV.L @(2*,R0),R1 ;Before execution (R0+8) = H'12345670
 ;After execution R1 = H'12345670
MOV.L R0,@(H'F,R1) ;Before execution R0 = H'FFFF7F80
 ;After execution (R1+60) = H'FFFF7F80
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Possible Exceptions:
• Data TLB multiple-hit exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
• Initial page write exception (only write operation)
Rev. 1.50, 10/04, page 367 of 610
11.1.34 MOVA (Move Effective Address): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVA
@(disp*,PC),R0
disp × 4 + PC & H'FFFFFFFC
+ 4 → R0
11000111dddddddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Description: This instruction stores the source operand effective address in general register R0.
The 8-bit displacement is multiplied by four after zero-extension. The PC value is the address of
this instruction, but a value with the lower 2 bits adjusted to B'00 is used in address calculation.
Notes: If this instruction is executed in a delay slot, a slot illegal instruction exception will be
generated.
Operation:
MOVA(int d) /* MOVA @(disp,PC),R0 */
{
 unsigned int disp;
 disp = (unsigned int)(0x000000FF & d);
 R[0] = (PC&0xFFFFFFFC) + 4 + (disp<<2);
 PC += 2;
}
Example:
Address .org H'1006
1006 MOVA STR*,R0 ;STR address → R0
1008 MOV.B @R0,R1 ;R1 = "X" ← Position after adjustment of lower 2 bits of PC
100A ADD R4,R5
 .align 4
100C STR:.sdata "XYZP12"
Note: * The assembler of Renesas Technology uses the value after scaling (×1, ×2, or ×4) as
the displacement (disp).
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 368 of 610
11.1.35 MOVCA.L (Move with Cache Block Allocation): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVCA.L R0,@Rn R0 → (Rn)
(without fetching cache block)
0000nnnn11000011 1 —
Description: This instruction stores the contents of general register R0 in the memory location
indicated by effective address Rn. This instruction differs from other store instructions as follows.
If write-back is selected for the accessed memory, and a cache miss occurs, the cache block will
be allocated but an R0 data write will be performed to that cache block without performing a block
read. Other cache block contents are undefined.
Notes: None
Operation:
MOVCAL(int n) /*MOVCA.L R0,@Rn */
 {
 if ((is_write_back_memory(R[n]))
 && (look_up_in_operand_cache(R[n]) == MISS))
 allocate_operand_cache_block(R[n]);
 Write_Long(R[n], R[0]);
 PC += 2;
 }
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Rev. 1.50, 10/04, page 369 of 610
11.1.36 MOVCO (Move Conditional): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVCO.L R0,@Rn LDST → T
if (T==1) R0 → (Rn)
0 → LDST
0000nnnn01110011 1 LDST
Description: MOVCO is used in combination with MOVLI to realize an atomic read-modifywrite operation in a single processor.
This instruction copies the value of the LDST flag to the T bit. When the T bit is set to 1, the value
of R0 is stored at the address in Rm. If the T bit is cleared to 0, the value is not stored at the
address in Rm. Finally, the LDST flag is cleared to 0. Since the LDST flag is cleared by an
instruction or exception, storage by the MOVCO instruction only proceeds when no interrupt or
exception has occurred between the execution of the MOVLI and MOVCO instructions.
Notes: None
Operation:
MOVCO(long n) /* MOVCO Rn,@Rn */
{
 T = LDST;
 if(T==1)
 Write_Long(R[n],R[0]);
 LDST = 0;
 PC += 2
}
Rev. 1.50, 10/04, page 370 of 610
Example:
Retry: MOVLI.L @Rn,R0 ; Atomic incrementation
 ADD #1,R0
 MOVCO.L R0,@Rn
 BF Retry ; Reexecute if an interrupt or other
 exception occurs between the MOVLI and
 MOVCO instructions
 NOP
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Rev. 1.50, 10/04, page 371 of 610
11.1.37 MOVLI (Move Linked): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVLI.L @Rm,R0 1 → LDST
(Rm) → R0
If an interrupt or exception has
occurred
0 → LDST
0000nnnn01100011 1 —
Description: MOVLI is used in combination with MOVCO to realize an atomic read-modifywrite operation in a single processor.
This instruction sets the LDST flag to 1 and reads the four bytes of data indicated by Rm into R0.
If, however, an interrupt or exception occurs, LDST is cleared to 0.
Storage by the MOVCO instruction only proceeds when the instruction is executed after the LDST
bit has been set by the MOVLI instruction and not cleared by an interrupt or other exception.
When LDST has been cleared to 0, the MOVCO instruction clears the T bit and does not proceed
with storage.
Notes: None
Operation:
MOVLINK(long m) /* MOVLI Rm,@Rn */
{
 LDST = 1;
 R[0] = Read_Long(R[m]);
 PC += 2
}
Example:
See the examples for the MOVCO instruction.
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 372 of 610
11.1.38 MOVT (Move T Bit): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVT Rn T → Rn 0000nnnn00101001 1 —
Description: This instruction stores the T bit in general register Rn. When T = 1, Rn = 1; when T
= 0, Rn = 0.
Notes: None
Operation:
MOVT(long n) /* MOVT Rn */
{
 R[n] = (0x00000001 & SR);
 PC += 2;
}
Example:
XOR R2,R2 ;R2 = 0
CMP/PZ R2 ;T = 1
MOVT R0 ;R0 = 1
CLRT ;T = 0
MOVT R1 ;R1 = 0
Rev. 1.50, 10/04, page 373 of 610
11.1.39 MOVUA (Move Unaligned): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVUA.L @Rm,R0 (Rm) → R0
Load non-boundary-aligned
data
0100nnnn10101001 2 —
MOVUA.L @Rm+,R0 (Rm) → R0, Rm + 4 → Rm
Load non-boundary-aligned
data
0100nnnn11101001 2 —
Description: This instruction loads the longword of data from the effective address indicated by
the contents of Rm in memory to R0. The address is not restricted to longword boundaries address
(4n); this instruction allows loading from non-longword-boundary addresses (4n + 1, 4n + 2, and
4n + 3). Data address error exceptions do not occur when access is to non-longword-boundary
addresses (4n + 1, 4n + 2, and 4n + 3).
Notes: None
Operation:
MOVUAL(int n) /* MOVUA.L Rm,R0*/
{
 Read_Unaligned_Long(R0,R[n]);
 PC += 2;
}
MOVUALP(int n) /* MOVUA.L Rm+,R0*/
{
 Read_Unaligned_Long(R0,R[n]);
 if(n != 0) R[n] += 4;
 PC += 2;
}
Rev. 1.50, 10/04, page 374 of 610
Example:
MOVUA.L @R1,R0 ;Before execution R1=H'00001001, R0=H'00000000
 ;After execution R0=(H'00001001)
MOVUA.L @R1+,R0 ;Before execution R1=H'00001007, R0=H'00000000
 ;After execution R1=H'0000100B, R0=(H'00001007)
; Special case in which the source operand is @R0
MOVUA.L @R0,R0 ;Before execution R0=H'00001001
 ;After execution R0=(H'00001001)
MOVUA.L @R0+,R0 ;Before execution R0=H'00001001
 ;After execution R0=(H'00001001)
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error (when the privileged area is accessed from user)
Rev. 1.50, 10/04, page 375 of 610
11.1.40 MUL.L (Multiply Long): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MUL.L Rm,Rn Rn × Rm → MACL 0000nnnnmmmm0111 2 —
Description: This instruction performs 32-bit multiplication of the contents of general registers
Rn and Rm, and stores the lower 32 bits of the result in the MACL register. The contents of
MACH are not changed.
Notes: None
Operation:
MULL(long m, long n) /* MUL.L Rm,Rn */
{
 MACL = R[n]*R[m];
 PC += 2;
}
Example:
MUL.L R0,R1 ;Before execution R0 = H'FFFFFFFE, R1 = H'00005555
 ;After execution MACL = H'FFFF5556
STS MACL,R0 ;Get operation result
Rev. 1.50, 10/04, page 376 of 610
11.1.41 MULS.W (Multiply as Signed Word): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MULS.W Rm,Rn Signed, Rn × Rm → MACL 0010nnnnmmmm1111 1 —
Description: This instruction performs 16-bit multiplication of the contents of general registers
Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as a
signed arithmetic operation. The contents of MACH are not changed.
Notes: None
Operation:
MULS(long m, long n) /* MULS Rm,Rn */
{
 MACL = ((long)(short)R[n]*(long)(short)R[m]);
 PC += 2;
}
Example:
MULS.W R0,R1 ;Before execution R0 = H'FFFFFFFE, R1 = H'00005555
 ;After execution MACL = H'FFFF5556
STS MACL,R0 ;Get operation result
Rev. 1.50, 10/04, page 377 of 610
11.1.42 MULU.W (Multiply as Unsigned Word): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 0010nnnnmmmm1110 1 —
Description: This instruction performs 16-bit multiplication of the contents of general registers
Rn and Rm, and stores the 32-bit result in the MACL register. The multiplication is performed as
an unsigned arithmetic operation. The contents of MACH are not changed.
Notes: None
Operation:
MULU(long m, long n) /* MULU Rm,Rn */
{
 MACL = (unsigned long)(unsigned short)R[n]*
 (unsigned long)(unsigned short)R[m];
 PC += 2;
}
Example:
MULU.W R0,R1 ;Before execution R0 = H'00000002, R1 = H'FFFFAAAA
 ;After execution MACL = H'00015554
STS MACL,R0 ;Get operation result
Rev. 1.50, 10/04, page 378 of 610
11.1.43 NEG (Negate): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
NEG Rm,Rn 0 - Rm → Rn 0110nnnnmmmm1011 1 —
Description: This instruction finds the two's complement of the contents of general register Rm
and stores the result in Rn. That is, it subtracts Rm from 0 and stores the result in Rn.
Notes: None
Operation:
NEG(long m, long n) /* NEG Rm,Rn */
{
 R[n] = 0-R[m];
 PC += 2;
}
Example:
NEG R0,R1 ;Before execution R0 = H'00000001
 ;After execution R1 = H'FFFFFFFF
Rev. 1.50, 10/04, page 379 of 610
11.1.44 NEGC (Negate with Carry): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
NEGC Rm,Rn 0 – Rm – T → Rn,
borrow → T
0110nnnnmmmm1010 1 Borrow
Description: This instruction subtracts the contents of general register Rm and the T bit from 0
and stores the result in Rn. A borrow resulting from the operation is reflected in the T bit. The
NEGC instruction is used for sign inversion of a value exceeding 32 bits.
Notes: None
Operation:
NEGC(long m, long n) /* NEGC Rm,Rn */
{
 unsigned long temp;
 temp = 0-R[m];
 R[n] = temp-T;
 if (0<temp) T = 1;
 else T = 0;
 if (temp<R[n]) T = 1;
 PC += 2;
}
Example:
CLRT ;Sign inversion of R0:R1 (64 bits)
NEGC R1,R1 ;Before execution R1 = H'00000001, T = 0
 ;After execution R1 = H'FFFFFFFF, T = 1
NEGC R0,R0 ;Before execution R0 = H'00000000, T = 1
 ;After execution R0 = H'FFFFFFFF, T = 1
Rev. 1.50, 10/04, page 380 of 610
11.1.45 NOP (No Operation): System Control Instruction
Format Operation Instruction Code Cycle T Bit
NOP No operation 0000000000001001 1 —
Description: This instruction simply increments the program counter (PC), advancing the
processing flow to execution of the next instruction.
Notes: None
Operation:
NOP( ) /* NOP */
{
 PC += 2;
}
Example:
NOP ;Time equivalent to one execution state elapses.
Rev. 1.50, 10/04, page 381 of 610
11.1.46 NOT (Not-logical Complement): Logical Instruction
Format Operation Instruction Code Cycle T Bit
NOT Rm,Rn ∼Rm → Rn 0110nnnnmmmm0111 1 —
Description: This instruction finds the one's complement of the contents of general register Rm
and stores the result in Rn. That is, it inverts the Rm bits and stores the result in Rn.
Notes: None
Operation:
NOT(long m, long n) /* NOT Rm,Rn */
{
 R[n] = ∼R[m];
 PC += 2;
}
Example:
NOT R0,R1 ;Before execution R0 = H'AAAAAAAA
 ;After execution R1 = H'55555555
Rev. 1.50, 10/04, page 382 of 610
11.1.47 OCBI (Operand Cache Block Invalidate): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
OCBI @Rn Operand cache block
invalidation
0000nnnn10010011 1 —
Description: This instruction accesses data using the contents indicated by effective address Rn.
In the case of a hit in the cache, the corresponding cache block is invalidated (the V bit is cleared
to 0). If there is unwritten information (U bit = 1), write-back is not performed even if write-back
mode is selected. No operation is performed in the case of a cache miss or an access to a noncache area.
Notes: None
Operation:
OCBI(int n) /* OCBI @Rn */
{
 invalidate_operand_cache_block(R[n]);
 PC += 2;
}
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Note that the above exceptions are generated even if OCBI does not operate.
Rev. 1.50, 10/04, page 383 of 610
11.1.48 OCBP (Operand Cache Block Purge): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
OCBP @Rn Writes back and invalidates
operand cache block
0000nnnn10100011 1 —
Description: This instruction accesses data using the contents indicated by effective address Rn. If
the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is
written back to external memory and that block is invalidated (the V bit is cleared to 0). If there is
no unwritten information (U bit = 0), the block is simply invalidated. No operation is performed in
the case of a cache miss or an access to a non-cache area.
Notes: None
Operation:
OCBP(int n) /* OCBP @Rn */
{
 if(is_dirty_block(R[n])) write_back(R[n])
 invalidate_operand_cache_block(R[n]);
 PC += 2;
}
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Note that the above exceptions are generated even if OCBP does not operate.
Rev. 1.50, 10/04, page 384 of 610
11.1.49 OCBWB (Operand Cache Block Write Back): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
OCBWB @Rn Writes back operand cache
block
0000nnnn10110011 1 —
Description: This instruction accesses data using the contents indicated by effective address Rn. If
the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is
written back to external memory and that block is cleaned (the U bit is cleared to 0). In other cases
(i.e. in the case of a cache miss or an access to a non-cache area, or if the block is already clean),
no operation is performed.
Notes: None
Operation:
OCBWB(int n) /* OCBWB @Rn */
 {
 if(is_dirty_block(R[n])) write_back(R[n]);
 PC += 2;
 }
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Note that the above exceptions are generated even if OCBWB does not operate.
Rev. 1.50, 10/04, page 385 of 610
11.1.50 OR (OR Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1 —
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1 —
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm
→ (R0 + GBR)
11001111iiiiiiii 3 —
Description:This instruction ORs the contents of general registers Rn and Rm and stores the
result in Rn.
This instruction can be used to OR general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to OR 8-bit memory with 8-bit
immediate data.
Notes: None
Rev. 1.50, 10/04, page 386 of 610
Operation:
OR(long m, long n) /* OR Rm,Rn */
{
 R[n] |= R[m];
 PC += 2;
}
ORI(long i) /* OR #imm,R0 */
{
 R[0] |= (0x000000FF & (long)i);
 PC += 2;
}
ORM(long i) /* OR.B #imm,@(R0,GBR) */
{
 long temp;
 temp = (long)Read_Byte(GBR+R[0]);
 temp |= (0x000000FF & (long)i);
 Write_Byte(GBR+R[0],temp);
 PC += 2;
}
Example:
OR R0,R1 ;Before execution R0 = H'AAAA5555, R1 = H'55550000
 ;After execution R1 = H'FFFF5555
OR #H'F0,R0 ;Before execution R0 = H'00000008
 ;After execution R0 = H'000000F8
OR.B #H'50,@(R0,GBR) ;Before execution (R0,GBR) = H'A5
 ;After execution (R0,GBR) = H'F5
Rev. 1.50, 10/04, page 387 of 610
Possible Exceptions: Exceptions may occur when OR.B instruction is executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Exceptions are checked taking a data access by this instruction as a byte load and a byte store.
Rev. 1.50, 10/04, page 388 of 610
11.1.51 PREF (Prefetch Data to Cache): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
PREF @Rn (Rn) → operand cache 0000nnnn10000011 1 —
Description: This instruction reads a 32-byte data block starting at a 32-byte boundary into the
operand cache. The lower 5 bits of the address specified by Rn are masked to zero.
This instruction does not generate data address error and MMU exceptions except data TLB
multiple-hit exception. In the event of an error, the PREF instruction is treated as an NOP (no
operation) instruction.
Notes: None
Operation:
PREF(int n) /* PREF @Rn */
{
 PC += 2;
}
Example:
 MOV.L #SOFT_PF,R1 ;R1 address is SOFT_PF
 PREF @R1 ;Load SOFT_PF data into on-chip cache
 .align 32
SOFT_PF: .data.l H'12345678
 .data.l H'9ABCDEF0
 .data.l H'AAAA5555
 .data.l H'5555AAAA
 .data.l H'11111111
 .data.l H'22222222
 .data.l H'33333333
 .data.l H'44444444
Possible Exceptions:
• Data TLB multiple-hit exception
Rev. 1.50, 10/04, page 389 of 610
11.1.52 PREFI (Prefetch Instruction Cache Block): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
PREFI @Rn Invalidation of instruction
cache indicated by logical
address Rn
0000nnnn11010011 10 —
Description: This instruction reads a 32-byte block of data starting at a 32-byte boundary within
the instruction cache. The lower 5 bits of the address specified by Rn are masked by zeroes.
This instruction does not generate data address error and MMU exceptions. In the event of an
error, the PREFI instruction is treated as an NOP (no operation) instruction.
When the address to be prefetched is missing from UTLB or is protected, the PREFI instruction is
treated as an NOP instruction and a TLB exception does not occur.
Notes: None
Operation:
PREFI(int n) /* PREFI @Rn*/
{
 prefetch_instruction_cache_block(R[n]);
 PC += 2;
}
Example:
 MOVA WakeUp,R0 ; Wakeup address
 PREFI @R0 ; Prefetching of instructions to be
 executed after release from the SLEEP state
 SLEEP
WakeUp:
 NOP
This instruction is used, before the SLEEP command is issued, to
prefetch instructions for execution on return from the SLEEP state.
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 390 of 610
11.1.53 ROTCL (Rotate with Carry Left): Shift Instruction
Format Operation Instruction Code Cycle T Bit
ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB
Description: This instruction rotates the contents of general register Rn one bit to the left through
the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.
MSB LSB
ROTCL T
Notes: None
Operation:
ROTCL(long n) /* ROTCL Rn */
{
 long temp;
 if ((R[n] & 0x80000000)==0) temp=0;
 else temp = 1;
 R[n] <<= 1;
 if (T==1) R[n] |= 0x00000001;
 else R[n] &= 0xFFFFFFFE;
 if (temp==1) T = 1;
 else T = 0;
 PC += 2;
}
Example:
ROTCL R0 ;Before execution R0 = H'80000000, T = 0
 ;After execution R0 = H'00000000, T = 1
Rev. 1.50, 10/04, page 391 of 610
11.1.54 ROTCR (Rotate with Carry Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB
Description: This instruction rotates the contents of general register Rn one bit to the right
through the T bit, and stores the result in Rn. The bit rotated out of the operand is transferred to
the T bit.
T
MSB LSB
ROTCR
Notes: None
Operation:
ROTCR(long n) /* ROTCR Rn */
{
 long temp;
 if ((R[n] & 0x00000001)==0) temp = 0;
 else temp = 1;
 R[n] >>= 1;
 if (T==1) R[n] |= 0x80000000;
 else R[n] &= 0x7FFFFFFF;
 if (temp==1) T = 1;
 else T = 0;
 PC += 2;
}
Example:
ROTCR R0 ;Before execution R0 = H'00000001, T = 1
 ;After execution R0 = H'80000000, T = 1
Rev. 1.50, 10/04, page 392 of 610
11.1.55 ROTL (Rotate Left): Shift Instruction
Format Operation Instruction Code Cycle T Bit
ROTL Rn T ← Rn ← MSB 0100nnnn00000100 1 MSB
Description: This instruction rotates the contents of general register Rn one bit to the left, and
stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.
MSB LSB
ROTL T
Notes: None
Operation:
ROTL(long n) /* ROTL Rn */
{
 if ((R[n]&0x80000000)==0) T = 0;
 else T = 1;
 R[n] <<= 1;
 if (T==1) R[n] |= 0x00000001;
 else R[n] &= 0xFFFFFFFE;
 PC += 2;
}
Example:
ROTL R0 ;Before execution R0 = H'80000000, T = 0
 ;After execution R0 = H'00000001, T = 1
Rev. 1.50, 10/04, page 393 of 610
11.1.56 ROTR (Rotate Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB
Description: This instruction rotates the contents of general register Rn one bit to the right, and
stores the result in Rn. The bit rotated out of the operand is transferred to the T bit.
MSB LSB
ROTR T
Notes: None
Operation:
ROTR(long n) /* ROTR Rn */
{
 if ((R[n] & 0x00000001)==0) T = 0;
 else T = 1;
 R[n] >>= 1;
 if (T==1) R[n] |= 0x80000000;
 else R[n] &= 0x7FFFFFFF;
 PC += 2;
}
Example:
ROTR R0 ;Before execution R0 = H'00000001, T = 0
 ;After execution R0 = H'80000000, T = 1
Rev. 1.50, 10/04, page 394 of 610
11.1.57 RTE (Return from Exception): System Control Instruction
Format Operation Instruction Code Cycle T Bit
RTE SSR → SR, SPC→ PC 0000000000101011 4 —
Description: This instruction returns from an exception or interrupt handling routine by restoring
the PC and SR values from SPC and SSR. Program execution continues from the address specified
by the restored PC value.
RTE is a privileged instruction, and can only be used in privileged mode. Use of this instruction in
user mode will cause an illegal instruction exception.
Notes: As this is a delayed branch instruction, the instruction following the RTE instruction is
executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. An exception
must not be generated by the instruction in this instruction's delay slot. If the following instruction
is a branch instruction, it is identified as a slot illegal instruction.
If this instruction is located in the delay slot immediately following a delayed branch instruction, it
is identified as a slot illegal instruction.
The SR value accessed by the instruction in the RTE delay slot is the value restored from SSR by
the RTE instruction. The SR and MD values defined prior to RTE execution are used to fetch the
instruction in the RTE delay slot.
Operation:
RTE( ) /* RTE */
{
 unsigned int temp;
 temp = PC;
 SR = SSR;
 PC = SPC;
 Delay_Slot(temp+2);
}
Example:
RTE ;Return to original routine.
ADD #8,R14 ;Executed before branch.
Rev. 1.50, 10/04, page 395 of 610
Note: In a delayed branch, the actual branch operation occurs after execution of the slot
instruction, but instruction execution (register updating, etc.) is in fact performed in
delayed branch instruction → delay slot instruction order. For example, even if the register
holding the branch destination address is modified in the delay slot, the branch destination
address will still be the register contents prior to the modification.
Possible Exceptions:
• General illugal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 396 of 610
11.1.58 RTS (Return from Subroutine): Branch Instruction
Format Operation Instruction Code Cycle T Bit
RTS PR → PC 0000000000001011 1 —
Description: This instruction returns from a subroutine procedure by restoring the PC from PR.
Processing continues from the address indicated by the restored PC value. This instruction can be
used to return from a subroutine procedure called by a BSR or JSR instruction to the source of the
call.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
The instruction that restores PR must be executed before the RTS instruction. This restore
instruction cannot be in the RTS delay slot.
Operation:
RTS( ) /* RTS */
{
 unsigned int temp;
 temp = PC;
 PC = PR;
 Delay_Slot(temp+2);
}
Rev. 1.50, 10/04, page 397 of 610
Example:
 MOV.L TABLE,R3 ;R3 = TRGET address
 JSR @R3 ; Branch to TRGET.
 NOP ;NOP executed before branch.
 ADD R0,R1 ;← Subroutine procedure return destination (PR contents)
 ........
TABLE: .data.l TRGET ;Jump table
 ........
TRGET: MOV R1,R0 ;← Entry to procedure
 RTS ;PR contents → PC
 MOV #12,R0 ;MOV executed before branch.
Possible Exceptions:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 398 of 610
11.1.59 SETS (Set S Bit): System Control Instruction
Format Operation Instruction Code Cycle T Bit
SETS 1 → S 0000000001011000 1 —
Description: This instruction sets the S bit to 1.
Notes: None
Operation:
SETS( ) /* SETS */
{
 S = 1;
 PC += 2;
}
Example:
SETS ;Before execution S = 0
 ;After execution S = 1
Rev. 1.50, 10/04, page 399 of 610
11.1.60 SETT (Set T Bit): System Control Instruction
Format Operation Instruction Code Cycle T Bit
SETT 1 → T 0000000000011000 1 1
Description: This instruction sets the T bit to 1.
Notes: None
Operation:
SETT( ) /* SETT */
{
 T = 1;
 PC += 2;
}
Example:
SETT ;Before execution T = 0
 ;After execution T = 1
Rev. 1.50, 10/04, page 400 of 610
11.1.61 SHAD (Shift Arithmetic Dynamically): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHAD Rm, Rn When Rm ≥ 0,
Rn << Rm → Rn
When Rm < 0,
Rn >> Rm → [MSB → Rn]
0100nnnnmmmm1100 1 —
Description: This instruction arithmetically shifts the contents of general register Rn. General
register Rm specifies the shift direction and the number of bits to be shifted.
Rn register contents are shifted to the left if the Rm register value is positive, and to the right if
negative. In a shift to the right, the MSB is added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If
the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left
shift range is 0 to 31, and the right shift range, 1 to 32.
MSB LSB
0
MSB
Rm ≥ 0
Rm < 0
MSB LSB
Notes: None
Rev. 1.50, 10/04, page 401 of 610
Operation:
SHAD(int m, int n) /*SHAD Rm,Rn */
{
 int sgn = R[m] & 0x80000000;
 if (sgn==0)
 R[n] <<= (R[m] & 0x1F);
 else if ((R[m] & 0x1F) == 0) {
 if ((R[n] & 0x80000000) == 0)
 R[n] = 0;
 else
 R[n] = 0xFFFFFFFF;
 }
 else
 R[n] = (long)R[n] >> ((~R[m] & 0x1F)+1);
 PC += 2;
}
Example:
SHAD R1,R2 ;Before execution R1 = H'FFFFFFEC, R2 = H'80180000
 ;After execution R1 = H'FFFFFFEC, R2 = H'FFFFF801
SHAD R3,R4 ;Before execution R3 = H'00000014, R4 = H'FFFFF801
 ;After execution R3 = H'00000014, R4 = H'80100000
Rev. 1.50, 10/04, page 402 of 610
11.1.62 SHAL (Shift Arithmetic Left): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB
Description:
This instruction arithmetically shifts the contents of general register Rn one bit to the left, and
stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.
MSB LSB
SHAL T 0
Notes: None
Operation:
SHAL(long n) /* SHAL Rn (Same as SHLL) */
{
 if ((R[n]&0x80000000)==0) T = 0;
 else T = 1;
 R[n] <<= 1;
 PC += 2;
}
Example:
SHAL R0 ;Before execution R0 = H'80000001, T = 0
 ;After execution R0 = H'00000002, T = 1
Rev. 1.50, 10/04, page 403 of 610
11.1.63 SHAR (Shift Arithmetic Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB
Description:
This instruction arithmetically shifts the contents of general register Rn one bit to the right, and
stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.
MSB LSB
SHAR T
Notes: None
Operation:
SHAR(long n) /* SHAR Rn */
{
 long temp;
 if ((R[n]&0x00000001)==0) T = 0;
 else T = 1;
 if ((R[n]&0x80000000)==0) temp = 0;
 else temp = 1;
 R[n] >>= 1;
 if (temp==1) R[n] |= 0x80000000;
 else R[n] &= 0x7FFFFFFF;
 PC += 2;
}
Example:
SHAR R0 ;Before execution R0 = H'80000001, T = 0
 ;After execution R0 = H'C0000000, T = 1
Rev. 1.50, 10/04, page 404 of 610
11.1.64 SHLD (Shift Logical Dynamically): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLD Rm, Rn When Rm ≥ 0,
Rn << Rm → Rn
When Rm < 0,
Rn >> Rm → [0 → Rn]
0100nnnnmmmm1101 1 —
Description: This instruction logically shifts the contents of general register Rn. General register
Rm specifies the shift direction and the number of bits to be shifted.
Rn register contents are shifted to the left if the Rm register value is positive, and to the right if
negative. In a shift to the right, 0s are added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If
the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left
shift range is 0 to 31, and the right shift range, 1 to 32.
MSB LSB
MSB
0
LSB
0
Rm ≥ 0
Rm < 0
Notes: None
Rev. 1.50, 10/04, page 405 of 610
Operation:
SHLD(int m, int n)/*SHLD Rm,Rn */
{
 int sgn = R[m] & 0x80000000;
 if (sgn == 0)
 R[n] <<= (R[m] & 0x1F);
 else if ((R[m] & 0x1F) == 0)
 R[n] = 0;
 else
 R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F)+1);
 PC += 2;
}
Example:
SHLD R1, R2 ;Before execution R1 = H'FFFFFFEC, R2 = H'80180000
 ;After execution R1 = H'FFFFFFEC, R2 = H'00000801
SHLD R3, R4 ;Before execution R3 = H'00000014, R4 = H'FFFFF801
 ;After execution R3 = H'00000014, R4 = H'80100000
Rev. 1.50, 10/04, page 406 of 610
11.1.65 SHLL (Shift Logical Left ): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB
Description: This instruction logically shifts the contents of general register Rn one bit to the left,
and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.
MSB LSB
SHLL T 0
Notes: None
Operation:
SHLL(long n) /* SHLL Rn (Same as SHAL) */
{
 if ((R[n]&0x80000000)==0) T = 0;
 else T = 1;
 R[n] <<= 1;
 PC += 2;
}
Example:
SHLL R0 ;Before execution R0 = H'80000001, T = 0
 ;After execution R0 = H'00000002, T = 1
Rev. 1.50, 10/04, page 407 of 610
11.1.66 SHLLn (n bits Shift Logical Left): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLL2 Rn Rn<<2 → Rn 0100nnnn00001000 1 —
SHLL8 Rn Rn<<8 → Rn 0100nnnn00011000 1 —
SHLL16 Rn Rn<<16 → Rn 0100nnnn00101000 1 —
Description: This instruction logically shifts the contents of general register Rn 2, 8, or 16 bits to
the left, and stores the result in Rn. The bits shifted out of the operand are discarded.
MSB LSB
0
SHLL8
SHLL16 MSB LSB
0
MSB LSB
0
SHLL2
Notes: None
Rev. 1.50, 10/04, page 408 of 610
Operation:
SHLL2(long n) /* SHLL2 Rn */
{
 R[n] <<= 2;
 PC += 2;
}
SHLL8(long n) /* SHLL8 Rn */
{
 R[n] <<= 8;
 PC += 2;
}
SHLL16(long n) /* SHLL16 Rn */
{
 R[n] <<= 16;
 PC += 2;
}
Example:
SHLL2 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'48D159E0
SHLL8 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'34567800
SHLL16 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'56780000
Rev. 1.50, 10/04, page 409 of 610
11.1.67 SHLR (Shift Logical Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB
Description: This instruction logically shifts the contents of general register Rn one bit to the
right, and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.
MSB LSB
SHLR 0 T
Notes: None
Operation:
SHLR(long n) /* SHLR Rn */
{
 if ((R[n] & 0x00000001)==0) T = 0;
 else T = 1;
 R[n] >>= 1;
 R[n] &= 0x7FFFFFFF;
 PC += 2;
}
Example:
SHLR R0 ;Before execution R0 = H'80000001, T = 0
 ;After execution R0 = H'40000000, T = 1
Rev. 1.50, 10/04, page 410 of 610
11.1.68 SHLRn (n bits Shift Logical Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLR2 Rn Rn>>2 → Rn 0100nnnn00001001 1 —
SHLR8 Rn Rn>>8 → Rn 0100nnnn00011001 1 —
SHLR16 Rn Rn>>16 → Rn 0100nnnn00101001 1 —
Description: This instruction logically shifts the contents of general register Rn 2, 8, or 16 bits to
the right, and stores the result in Rn. The bits shifted out of the operand are discarded.
MSB LSB
0
SHLR8
SHLR16 MSB LSB
0
MSB LSB
0
SHLR2
Notes: None
Rev. 1.50, 10/04, page 411 of 610
Operation:
SHLR2(long n) /* SHLR2 Rn */
{
 R[n] >>= 2;
 R[n] &= 0x3FFFFFFF;
 PC += 2;
}
SHLR8(long n) /* SHLR8 Rn */
{
 R[n] >>= 8;
 R[n] &= 0x00FFFFFF;
 PC += 2;
}
SHLR16(long n) /* SHLR16 Rn */
{
 R[n] >>= 16;
 R[n] &= 0x0000FFFF;
 PC += 2;
}
Example:
SHLR2 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'048D159E
SHLR8 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'00123456
SHLR16 R0 ;Before execution R0 = H'12345678
 ;After execution R0 = H'00001234
Rev. 1.50, 10/04, page 412 of 610
11.1.69 SLEEP (Sleep): System Control Instruction (Privileged Instruction)
Format Operation Instruction Code Cycle T Bit
SLEEP Sleep or standby 0000000000011011 Undefine
d
—
Description: This instruction places the CPU in the power-down state.
In power-down mode, the CPU retains its internal state, but immediately stops executing
instructions and waits for an interrupt request. When it receives an interrupt request, the CPU exits
the power-down state.
SLEEP is a privileged instruction, and can only be used in privileged mode. Use of this instruction
in user mode will cause an illegal instruction exception.
Notes: SLEEP performance depends on the standby control register (STBCR). See Power-Down
Modes in the target product's hardware manual, for details.
Operation:
SLEEP( ) /* SLEEP */
{
 Sleep_standby();
}
Example:
SLEEP ;Transition to power-down mode
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 413 of 610
11.1.70 STC (Store Control Register): System Control Instruction (Privileged Instruction)
Format Operation Instruction Code Cycle T Bit
STC GBR, Rn GBR → Rn 0000nnnn00010010 1 —
STC VBR, Rn VBR → Rn 0000nnnn00100010 1 —
STC SSR, Rn SSR → Rn 0000nnnn00110010 1 —
STC SPC, Rn SPC → Rn 0000nnnn01000010 1 —
STC SGR, Rn SGR → Rn 0000nnnn00111010 1 —
STC DBR, Rn DBR → Rn 0000nnnn11111010 1 —
STC R0_BANK, Rn R0_BANK → Rn 0000nnnn10000010 1 —
STC R1_BANK, Rn R1_BANK → Rn 0000nnnn10010010 1 —
STC R2_BANK, Rn R2_BANK → Rn 0000nnnn10100010 1 —
STC R3_BANK, Rn R3_BANK → Rn 0000nnnn10110010 1 —
STC R4_BANK, Rn R4_BANK → Rn 0000nnnn11000010 1 —
STC R5_BANK, Rn R5_BANK → Rn 0000nnnn11010010 1 —
STC R6_BANK, Rn R6_BANK → Rn 0000nnnn11100010 1 —
STC R7_BANK, Rn R7_BANK → Rn 0000nnnn11110010 1 —
STC.L GBR, @-Rn Rn-4 → Rn, GBR → (Rn) 0100nnnn00010011 1 —
STC.L VBR, @-Rn Rn-4 → Rn, VBR → (Rn) 0100nnnn00100011 1 —
STC.L SSR, @-Rn Rn-4 → Rn, SSR → (Rn) 0100nnnn00110011 1 —
STC.L SPC, @-Rn Rn-4 → Rn, SPC → (Rn) 0100nnnn01000011 1 —
STC.L SGR, @-Rn Rn-4 → Rn, SGR → (Rn) 0100nnnn00110010 1 —
STC.L DBR, @-Rn Rn-4 → Rn, DBR → (Rn) 0100nnnn11110010 1 —
STC.L R0_BANK, @-Rn Rn-4 → Rn, R0_BANK → (Rn) 0100nnnn10000011 1 —
STC.L R1_BANK, @-Rn Rn-4 → Rn, R1_BANK → (Rn) 0100nnnn10010011 1 —
STC.L R2_BANK, @-Rn Rn-4 → Rn, R2_BANK → (Rn) 0100nnnn10100011 1 —
STC.L R3_BANK, @-Rn Rn-4 → Rn, R3_BANK → (Rn) 0100nnnn10110011 1 —
STC.L R4_BANK, @-Rn Rn-4 → Rn, R4_BANK → (Rn) 0100nnnn11000011 1 —
STC.L R5_BANK, @-Rn Rn-4 → Rn, R5_BANK → (Rn) 0100nnnn11010011 1 —
STC.L R6_BANK, @-Rn Rn-4 → Rn, R6_BANK → (Rn) 0100nnnn11100011 1 —
STC.L R7_BANK, @-Rn Rn-4 → Rn, R7_BANK → (Rn) 0100nnnn11110011 1 —
Description: This instruction stores control register GBR, VBR, SSR, SPC, SGR, DBR or
Rm_BANK (m = 0–7) in the destination.
Rm_BANK operands are specified by the RB bit of the SR register:
when the RB bit is 1 Rm_BANK0 is accessed,
when the RB bit is 0 Rm_BANK1 is accessed.
Rev. 1.50, 10/04, page 414 of 610
Notes: STC/STC.L can only be used in privileged mode excepting STC GBR, Rn/STC.L GBR,
@-Rn. Use of these instructions in user mode will cause illegal instruction exceptions.
Operation:
STCGBR(int n) /* STC GBR,Rn */
 {
 R[n] = GBR;
 PC += 2;
 }
STCVBR(int n) /* STC VBR,Rn : Privileged */
 {
 R[n] = VBR;
 PC += 2;
 }
STCSSR(int n) /* STC SSR,Rn : Privileged */
 {
 R[n] = SSR;
 PC += 2;
 }
STCSPC(int n) /* STC SPC,Rn : Privileged */
 {
 R[n] = SPC;
 PC += 2;
 }
STCSGR(int n) /* STC SGR,Rn : Privileged */
 {
 R[n] = SGR;
 PC += 2;
 }
Rev. 1.50, 10/04, page 415 of 610
STCDBR(int n) /* STC DBR,Rn : Privileged */
 {
 R[n] = DBR;
 PC += 2;
 }
STCRm_BANK(int n) /* STC Rm_BANK,Rn : Privileged */
 /* m=0–7 */
 {
 R[n] = Rm_BANK;
 PC += 2;
 }
STCMGBR(int n) /* STC.L GBR,@–Rn */
 {
 R[n] –= 4;
 Write_Long(R[n],GBR);
 PC += 2;
 }
STCMVBR(int n) /* STC.L VBR,@-Rn : Privileged */
 {
 R[n] –= 4;
 Write_Long(R[n],VBR);
 PC += 2;
 }
STCMSSR(int n) /* STC.L SSR,@-Rn : Privileged */
 {
 R[n] –= 4;
 Write_Long(R[n],SSR);
 PC += 2;
 }
Rev. 1.50, 10/04, page 416 of 610
STCMSPC(int n) /* STC.L SPC,@-Rn : Privileged */
 {
 R[n] –= 4;
 Write_Long(R[n],SPC);
 PC += 2;
 }
STCMSGR(int n) /* STC.L SGR,@-Rn : Privileged */
 {
 R[n] –= 4;
 Write_Long(R[n],SGR);
 PC += 2;
 }
STCMDBR(int n) /* STC.L DBR,@-Rn : Privileged */
 {
 R[n] –= 4;
 Write_Long(R[n],DBR);
 PC += 2;
 }
STCMRm_BANK(int n) /* STC.L Rm_BANK,@-Rn : Privileged */
 /* m=0–7 */
 {
 R[n] –= 4;
 Write_Long(R[n],Rm_BANK);
 PC += 2;
 }
Possible Exceptions:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Rev. 1.50, 10/04, page 417 of 610
11.1.71 STS (Store System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
STS MACH,Rn MACH → Rn 0000nnnn00001010 1 —
STS MACL,Rn MACL → Rn 0000nnnn00011010 1 —
STS PR,Rn PR → Rn 0000nnnn00101010 1 —
STS.L MACH,@-Rn Rn - 4 → Rn, MACH → (Rn) 0100nnnn00000010 1 —
STS.L MACL,@-Rn Rn - 4 → Rn, MACL → (Rn) 0100nnnn00010010 1 —
STS.L PR,@-Rn Rn - 4 → Rn, PR → (Rn) 0100nnnn00100010 1 —
Description: This instruction stores system register MACH, MACL, or PR in the destination.
Notes: None
Operation:
STSMACH(int n) /* STS MACH,Rn */
{
 R[n] = MACH;
 PC += 2;
}
STSMACL(int n) /* STS MACL,Rn */
{
 R[n] = MACL;
 PC += 2;
}
STSPR(int n) /* STS PR,Rn */
{
 R[n] = PR;
 PC += 2;
}
Rev. 1.50, 10/04, page 418 of 610
STSMMACH(int n) /* STS.L MACH,@-Rn */
{
 R[n] –= 4;
 Write_Long(R[n],MACH);
 PC += 2;
}
STSMMACL(int n) /* STS.L MACL,@-Rn */
{
 R[n] –= 4;
 Write_Long(R[n],MACL);
 PC += 2;
}
STSMPR(int n) /* STS.L PR,@-Rn */
{
 R[n] –= 4;
 Write_Long(R[n],PR);
 PC += 2;
}
Example:
STS MACH,R0 ; Before execution R0 = H'FFFFFFFF, MACH = H'00000000
 ; After execution R0 = H'00000000
STS.L PR,@-R15 ; Before execution R15 = H'10000004
 ; After execution R15 = H'10000000, (R15) = PR
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Rev. 1.50, 10/04, page 419 of 610
11.1.72 SUB (Subtract Binary): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
SUB Rm,Rn Rn - Rm → Rn 0011nnnnmmmm1000 1 —
Description: This instruction subtracts the contents of general register Rm from the contents of
general register Rn and stores the result in Rn. For immediate data subtraction, ADD #imm,Rn
should be used.
Notes: None
Operation:
SUB(long m, long n) /* SUB Rm,Rn */
{
 R[n] -= R[m];
 PC += 2;
}
Example:
SUB R0,R1 ;Before execution R0 = H'00000001, R1 = H'80000000
 ;After execution R1 = H'7FFFFFFF
Rev. 1.50, 10/04, page 420 of 610
11.1.73 SUBC (Subtract with Carry): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
SUBC Rm,Rn Rn - Rm-T → Rn, borrow → T 0011nnnnmmmm1010 1 Borrow
Description: This instruction subtracts the contents of general register Rm and the T bit from the
contents of general register Rn, and stores the result in Rn. A borrow resulting from the operation
is reflected in the T bit. This instruction is used for subtractions exceeding 32 bits.
Notes: None
Operation:
SUBC(long m, long n) /* SUBC Rm,Rn */
{
 unsigned long tmp0,tmp1;
 tmp1 = R[n] - R[m];
 tmp0 = R[n];
 R[n] = tmp1 - T;
 if (tmp0<tmp1) T = 1;
 else T = 0;
 if (tmp1<R[n]) T = 1;
 PC += 2;
}
Example:
CLRT ;R0:R1(64 bits) – R2:R3(64 bits) = R0:R1(64 bits)
SUBC R3,R1 ;Before execution T = 0, R1 = H'00000000, R3 = H'00000001
 ;After execution T = 1, R1 = H'FFFFFFFF
SUBC R2,R0 ;Before execution T = 1, R0 = H'00000000, R2 = H'00000000
 ;After execution T = 1, R0 = H'FFFFFFFF
Rev. 1.50, 10/04, page 421 of 610
11.1.74 SUBV (Subtract with (V flag) Underflow Check): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
SUBV Rm,Rn Rn - Rm → Rn, underflow → T 0011nnnnmmmm1011 1 Underflow
Description: This instruction subtracts the contents of general register Rm from the contents of
general register Rn, and stores the result in Rn. If underflow occurs, the T bit is set.
Notes: None
Operation:
SUBV(long m, long n) /* SUBV Rm,Rn */
{
 long dest,src,ans;
 if ((long)R[n]>=0) dest = 0;
 else dest = 1;
 if ((long)R[m]>=0) src = 0;
 else src = 1;
 src += dest;
 R[n] -= R[m];
 if ((long)R[n]>=0) ans = 0;
 else ans = 1;
 ans += dest;
 if (src==1) {
 if (ans==1) T = 1;
 else T = 0;
 }
 else T = 0;
 PC += 2;
}
Example:
SUBV R0,R1 ;Before execution R0 = H'00000002, R1 = H'80000001
 ;After execution R1 = H'7FFFFFFF, T = 1
SUBV R2,R3 ;Before execution R2 = H'FFFFFFFE, R3 = H'7FFFFFFE
 ;After execution R3 = H'80000000, T = 1
Rev. 1.50, 10/04, page 422 of 610
11.1.75 SWAP (Swap Register Halves): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
SWAP.B Rm,Rn Rm → lower-2-byte upper-/
lower-byte swap → Rn
0110nnnnmmmm1000 1 —
SWAP.W Rm,Rn Rm → upper-/
lower-word swap → Rn
0110nnnnmmmm1001 1
Description: This instruction swaps the upper and lower parts of the contents of general register
Rm, and stores the result in Rn.
In the case of a byte specification, the 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits
from bit 7 to bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn.
In the case of a word specification, the 16 bits from bit 31 to bit 16 of Rm are swapped with the 16
bits from bit 15 to bit 0.
Notes: None
Operation:
SWAPB(long m, long n) /* SWAP.B Rm,Rn */
{
 unsigned long temp0,temp1;
 temp0 = R[m] & 0xFFFF0000;
 temp1 = (R[m] & 0x000000FF) << 8;
 R[n] = (R[m] & 0x0000FF00) >> 8;
 R[n] = R[n] | temp1 | temp0;
 PC += 2;
}
SWAPW(long m, long n) /* SWAP.W Rm,Rn */
{
 unsigned long temp;
 temp = (R[m]>>16)&0x0000FFFF;
 R[n] = R[m]<<16;
 R[n] |= temp;
 PC += 2;
}
Rev. 1.50, 10/04, page 423 of 610
Example:
SWAP.B R0,R1 ;Before execution R0 = H'12345678
 ;After execution R1 = H'12347856
SWAP.W R0,R1 ;Before execution R0 = H'12345678
 ;After execution R1 = H'56781234
Rev. 1.50, 10/04, page 424 of 610
11.1.76 SYNCO (Synchronize Data Operation): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
SYNCO Data accesses invoked by the
following instruction are not
executed until execution of data
accesses which precede this
instruction has been completed.
0000000010101011 Undefined —
Description: This instruction is used to synchronize data operations. When this instruction is
executed, the subsequent bus accesses are not executed until the execution of all preceding bus
accesses has been completed.
Notes: The SYNCO instruction can not guarantee the ordering of receipt timing which is notified
by the memory-mapped peripheral resources through the method except bus when the register is
changed by bus accesses. Refer to the description of each registers to guarantee this ordering.
Operation:
SYNCO() /* SYNCO*/
{
 synchronize_data_operaiton();
 PC += 2;
}
Example:
1. Ordering access to memory areas which are shared with other memory users
2. Flushing all write buffers
3. Stopping memory-access operations from merging and becoming ineffective
4. Waiting for the completion of cache-control instructions
Rev. 1.50, 10/04, page 425 of 610
11.1.77 TAS (Test And Set): Logical Instruction
Format Operation Instruction Code Cycle T Bit
TAS.B @Rn If (Rn) = 0, 1 → T, else 0 → T
1 → MSB of (Rn)
0100nnnn00011011 4 Test
result
Description: This instruction purges the cache block corresponding to the memory area specified
by the contents of general register Rn, reads the byte data indicated by that address, and sets the T
bit to 1 if that data is zero, or clears the T bit to 0 if the data is nonzero. The instruction then sets
bit 7 to 1 and writes to the same address. The bus is not released during this period.
The purge operation is executed as follows.
In a purge operation, data is accessed using the contents of general register Rn as the effective
address. If there is a cache hit and the corresponding cache block is dirty (U bit = 1), the contents
of that cache block are written back to external memory, and the cache block is then invalidated
(by clearing the V bit to 0). If there is a cache hit and the corresponding cache block is clean (U bit
= 0), the cache block is simply invalidated (by clearing the V bit to 0). A purge is not executed in
the event of a cache miss, or if the accessed memory location is non-cacheable.
The two TAS.B memory accesses are executed automatically. Another memory access is not
executed between the two TAS.B accesses.
Notes: None
Operation:
TAS(int n) /* TAS.B @Rn */
{
 int temp;
 temp = (int)Read_Byte(R[n]); /* Bus Lock */
 if (temp==0) T = 1;
 else T = 0;
 temp |= 0x00000080;
 Write_Byte(R[n],temp); /* Bus unlock */
 PC += 2;
}
Rev. 1.50, 10/04, page 426 of 610
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Exceptions are checked taking a data access by this instruction as a byte load and a byte store.
Rev. 1.50, 10/04, page 427 of 610
11.1.78 TRAPA (Trap Always): System Control Instruction
Format Operation Instruction Code Cycle T Bit
TRAPA #imm Imm<<2 → TRA, PC + 2 → SPC,
SR → SSR, R15 → SGR,
1 → SR.MD/BL/RB,
H'160 → EXPEVT,
VBR + H'00000100 → PC
11000011iiiiiiii 13 —
Description: This instruction starts trap exception handling. The values of (PC + 2), SR, and R15
are saved to SPC, SSR and SGR, and 8-bit immediate data is stored in the TRA register (bits 9 to
2). The processor mode is switched to privileged mode (the MD bit in SR is set to 1), and the BL
bit and RB bit in SR are set to 1. As a result, exception and interrupt requests are masked (not
accepted), and the BANK1 registers (R0_BANK1 to R7_BANK1) are selected. Exception code
H'160 is written to the EXPEVT register (bits 11 to 0). The program branches to address (VBR +
H'00000100), indicated by the sum of the VBR register contents and offset H'00000100.
Notes: None
Operation:
TRAPA(int i) /* TRAPA #imm */
 {
 int imm;
 imm = (0x000000FF & i);
 TRA = imm<<2;
 SSR = SR;
 SPC = PC+2;
 SGR = R15;
 SR.MD = 1;
 SR.BL = 1;
 SR.RB=1;
 EXPEVT = 0x00000160;
 PC = VBR + 0x00000100;
}
Possible Exceptions:
• Unconditional trap
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 428 of 610
11.1.79 TST (Test Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
TST Rm,Rn Rn & Rm; if result is 0,
1 → T, else 0 → T
0010nnnnmmmm1000 1 Test
result
TST #imm,R0 R0 & imm; if result is 0,
1 → T, else 0 → T
11001000iiiiiiii 1 Test
result
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
if result is 0, 1 → T,
else 0 → T
11001100iiiiiiii 3 Test
result
Description: This instruction ANDs the contents of general registers Rn and Rm, and sets the T
bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not
changed.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data. The contents of R0 or the memory are not changed.
Notes: None
Operation:
TST(long m, long n) /* TST Rm,Rn */
{
 if ((R[n]&R[m])==0) T = 1;
 else T = 0;
 PC += 2;
}
TSTI(long i) /* TST #imm,R0 */
{
 long temp;
 temp = R[0]&(0x000000FF & (long)i);
 if (temp==0) T = 1;
 else T = 0;
 PC += 2;
}
Rev. 1.50, 10/04, page 429 of 610
TSTM(long i) /* TST.B #imm,@(R0,GBR) */
{
 long temp;
 temp = (long)Read_Byte(GBR+R[0]);
 temp &= (0x000000FF & (long)i);
 if (temp==0) T = 1;
 else T = 0;
 PC += 2;
}
Example:
TST R0,R0 ;Before execution R0 = H'00000000
 ;After execution T = 1
TST #H'80,R0 ;Before execution R0 = H'FFFFFF7F
 ;After execution T = 1
TST.B #H'A5,@(R0,GBR) ;Before execution (R0,GBR) = H'A5
 ;After execution T = 0
Possible Exceptions: Exceptions may occur when TST.B instruction is executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Exceptions are checked taking a data access by this instruction as a byte load and a byte store.
Rev. 1.50, 10/04, page 430 of 610
11.1.80 XOR (Exclusive OR Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 1 —
XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii 1 —
XOR.B #imm,@(R0,GBR) (R0 + GBR)^imm →
(R0 + GBR)
11001110iiiiiiii 3 —
Description: This instruction exclusively ORs the contents of general registers Rn and Rm, and
stores the result in Rn.
This instruction can be used to exclusively OR register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to exclusively OR 8-bit memory
with 8-bit immediate data.
Notes: None
Operation:
XOR(long m, long n) /* XOR Rm,Rn */
{
 R[n] ^= R[m];
 PC += 2;
}
XORI(long i) /* XOR #imm,R0 */
{
 R[0] ^= (0x000000FF & (long)i);
 PC += 2;
}
XORM(long i) /* XOR.B #imm,@(R0,GBR) */
{
 int temp;
 temp = (long)Read_Byte(GBR+R[0]);
 temp ^= (0x000000FF &(long)i);
 Write_Byte(GBR+R[0],temp);
 PC += 2;
}
Rev. 1.50, 10/04, page 431 of 610
Example:
XOR R0,R1 ;Before execution R0 = H'AAAAAAAA, R1 = H'55555555
 ;After execution R1 = H'FFFFFFFF
XOR #H'F0,R0 ;Before execution R0 = H'FFFFFFFF
 ;After execution R0 = H'FFFFFF0F
XOR.B #H'A5,@(R0,GBR) ;Before execution (R0,GBR) = H'A5
 ;After execution (R0,GBR) = H'00
Possible Exceptions: Exceptions may occur when XOR.B instruction is executed.
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Exceptions are checked taking a data access by this instruction as a byte load and a byte store.
Rev. 1.50, 10/04, page 432 of 610
11.1.81 XTRCT (Extract): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
XTRCT Rm,Rn Middle 32 bits of Rm:Rn → Rn 0010nnnnmmmm1101 1 —
Description: This instruction extracts the middle 32 bits from the 64-bit contents of linked general
registers Rm and Rn, and stores the result in Rn.
MSB
Rm Rn
Rn
MSB LSB LSB
Notes: None
Operation:
XTRCT(long m, long n) /* XTRCT Rm,Rn */
{
 unsigned long temp;
 temp = (R[m]<<16) & 0xFFFF0000;
 R[n] = (R[n]>>16) & 0x0000FFFF;
 R[n] |= temp;
 PC += 2;
}
Example:
XTRCT R0,R1 ;Before execution R0 = H'01234567, R1 = H'89ABCDEF
 ;After execution R1 = H'456789AB
Rev. 1.50, 10/04, page 433 of 610
11.2 CPU Instructions (DSP related)
Of the SH4AL-DSP's CPU instructions, those which support the DSP or differ functionally from
those of the SH-4A are described in this section.
Rev. 1.50, 10/04, page 434 of 610
11.2.1 BSR (Branch to Subroutine): Branch Instruction (Delayed Branch Instruction)
Format Operation Instruction Code Cycle T Bit
BSR label PC + 4/6 → PR,
PC + 4 + disp × 2 → PC
1011dddddddddddd 1 
Description: This instruction branches to the address (PC + 4 + displacement × 2) and stores the
address (PC + 4) or (PC + 6) in the PR. When the delay-slot instruction of a BSR is a 32-bit DSP
instruction, 6 is added; in other cases, 4 is added. The PC's source value is the address of the BSR
instruction. The 12-bit displacement is sign-extended and doubled. Consequently, the relative
interval from the branch destination is –4096 to +4094 bytes. If this displacement is too small to
reach the branch destination, the JSR instruction must be used instead.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
branching. No interrupts are accepted between this instruction and the next instruction. If the next
instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation:
BSR(int d) /* BSR disp */
{
 int disp;
 unsigned int temp;
 temp = PC;
 if((d&0x800) == 0)
 disp = (0x00000FFF & d);
 else disp = (0xFFFFF000 | d);
 if(is_32bit_instruction(temp+2))
 PR = PC + 6;
 else PR = PC + 4;
 PC = PC + 4 + (disp << 1);
 Delay_Slot(temp + 2);
}
Rev. 1.50, 10/04, page 435 of 610
Examples:
 BSR TRGET ;Branches to TRGET
 MOV R3,R4 ;Executes the MOV instruction before branching
 ADD R0,R1 ;← Return address for when the subroutine procedure is
completed (PR data))
 .......
 .......
TRGET: ;← Procedure entrance
 MOV R2,R3
 RTS ;Returns to the above ADD instruction
 MOV #1,R0 ;Executes MOV before branching
Possible Exception:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 436 of 610
11.2.2 BSRF (Branch to Subroutine Far): Branch Instruction (Derayed Branch
Instruction)
Format Operation Instruction Code Cycle T Bit
BSRF Rn PC + 4/6 → PR,
PC + 4 + Rn → PC
0000nnnn00000011 1 
Description: This instruction branches to the address (PC + 4 + Rn) and stores the address (PC +
4) or (PC + 6) in the PR. When the delay-slot instruction of a BSRF is a 32-bit DSP instruction, 6
is added; in other cases, 4 is added. The PC's source value is the address of the BSRF instruction.
The branch destination is the address (PC + 4) + (32 bits of general register Rn).
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
branching. No interrupts are accepted between this instruction and the next instruction. If the next
instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation:
BSRF(int n) /* BSRF Rn */
{
 unsigned int temp;
 temp = PC;
 if(is_32bit_instruction(temp+2))
 PR = PC +6;
 else PR = PC + 4;
 PC = PC + 4 + R[n];
 Delay_Slot(temp+2);
}
Rev. 1.50, 10/04, page 437 of 610
Examples:
 MOV.L #(TARGET-BSRF_PC),R0 ;Sets displacement.
 BRSF @R0 ;Branches to TARGET
 MOV R3,R4 ;Executes the MOV instruction before
BSRF_PC: ;
 ADD R0,R1
 .....
TARGET: ;←Procedure entrance
 MOV R2,R3
 RTS ;Returns to the above ADD instruction
 MOV #1,R0 ;Executes MOV before branching
Possible Exception:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 438 of 610
11.2.3 CLRDMXY (Clear DMX DMY): System Control Instruction
Format Operation Instruction Code Cycle T Bit
CLRDMXY 0 → DMX (SR[10])
0 → DMY (SR[11])
0000000010001000 1 
Description: This instruction resets the DMX and DMY bits of the SR, and cancels X pointer
modulo addressing mode.
Note: When SR.DSP = 0, general illegal instruction exception occurs if CLRDMXY is executed
not in a delay slot, and slot illegal instruction occurs if CLRDMXY is executed in a delay slot.
Operation:
CLRDMXY( ) /* CLRDMXY */
{
 SR.DMX=0;
 SR.DMY=0;
 PC += 2;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 439 of 610
11.2.4 JSR (Jump to Subroutine): Branch Instruction (Delayed Branch Instruction)
Format Operation Instruction Code Cycle T Bit
JSR @Rn PC + 4/6 → PR, Rn → PC 0100nnnn00001011 1 —
Description: This instruction makes a delayed branch to the subroutine procedure at the specified
address after execution of the following instruction. Return address (PC + 4) or (PC + 6) is saved
in PR, and a branch is made to the address indicated by general register Rn. JSR is used in
combination with RTS for subroutine procedure calls.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
JSR(int n) /* JSR @Rn */
{
 unsigned int temp;
 temp = PC;
 if(is_32bit_instruction(temp+2))
 PR = PC +6;
 else PR = PC + 4;
 PC = R[n];
 Delay_Slot(temp+2);
}
Rev. 1.50, 10/04, page 440 of 610
Example:
 MOV.L JSR_TABLE,R0 ;R0 = TRGET address
 JSR @R0 ;Branch to TRGET.
 XOR R1,R1 ;XOR executed before branch.
 ADD R0,R1 ;← Procedure return destination (PR contents)
 .......
 .align 4
JSR_TABLE: .data.l TRGET ;Jump table
TRGET: NOP ;← Entry to procedure
 MOV R2,R3 ;
 RTS ;Return to above ADD instruction.
 MOV #70,R1 ;MOV executed before RTS.
Possible Exception:
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 441 of 610
11.2.5 LDC (Load to Control Register): System Control Instruction (Some of these
instructions are usable as privileged instructions.Privileged Only)
Format Operation Instruction Code Cycle T Bit
LDC Rm,SR Rm → SR 0100mmmm00001110 4 LSB
LDC Rm,MOD Rm → MOD 0100mmmm01011110 1 —
LDC Rm,RE Rm → RE 0100mmmm01111110 1 —
LDC Rm,RS Rm → RS 0100mmmm01101110 1 —
LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 4 LSB
LDC.L @Rm+,MOD (Rm) → MOD, Rm + 4 → Rm 0100mmmm01010111 1 —
LDC.L @Rm+,RE (Rm) → RE, Rm + 4 → Rm 0100mmmm01110111 1 —
LDC.L @Rm+,RS (Rm) → RS, Rm + 4 → Rm 0100mmmm01100111 1 —
Description: Stores source operand in control registers SR.
Notes: When the DSP bit of the SR register is cleared to 0, LDC Rm,SR and LDC.L @Rm,SR
become privileged instructions; this allows updating of all bits in the SR register. When the DSP
bit is set to 1 (in privileged DSP or user DSP mode) these instructions are not privileged and can
then be executed in user DSP mode. Note that only some bits (DSP-related bits) of the SR register
are writable in user DSP mode.
The other six instructions are executable in user mode.
When the LDC Rm,SR instruction or LDC.L @Rm+,SR instruction is placed in the delay-slot
immediately after a delayed branch instruction, the instructions are treated as slot illegal
instructions.
Operation:
LDCSR(long m) /* LDC Rm,SR : Privileged conditionally */
{
 if(SR.MD==1)
 {
 SR = R[m] & 0x7FFF1FFF;
 }
 else if(SR.DSP==1)
 {
 SR = SR & 700003F3 | R[m] & 0x0FFF1C0C;
 }
Rev. 1.50, 10/04, page 442 of 610
 PC += 2;
}
LDCMOD(long m) /* LDC Rm,MOD */
{
MOD = R[m];
PC += 2;
}
LDCRE(long m) /* LDC Rm,RE */
{
RE = R[m];
PC += 2;
}
LDCRS(long m) /* LDC Rm,RS */
{
RS = R[m];
PC += 2;
}
LDCMSR(long m)/* LDC.L @Rm+,SR : Privileged conditionally */
{
 if(SR.MD==1)
 {
 SR = Read_Long(R[m]) & 0x7FFF1FFF
 }
 else if(SR.DSP==1)
 {
 SR = SR & 700003F3 | Read_Long(R[m]) & 0x0FFF1C0C;
 }
 R[m] += 4;
 PC += 2;
}
Rev. 1.50, 10/04, page 443 of 610
LDCMMOD(long m)/*LDC.L @Rm+,MOD */
{
MOD = Read_Long(R[m]);
R[m] += 4;
PC += 2;
}
LDCMRE(long m) /*LDC.L @Rm+,RE */
{
RE = Read_Long(R[m]);
R[m] += 4;
PC += 2;
}
LDCMRS(long m) /*LDC.L @Rm+,RS */
{
RS = Read_Long(R[m]);
R[m] += 4;
PC += 2;
}
Examples:
LDC R0,SR ;Before execution R0 = H'FFFFFFFF, SR = H'00000000
 ;After execution SR = H'70001FFF, T = 1
LDC.L @R15+,GBR ;Before execution R15 = H'10000000, @R15 + H'12345678,
 GBR = H'EDCBA987
 ;After execution R15 = H'10000004, GBR = @H'10000000
Possible Exceptins:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 444 of 610
11.2.6 LDRC (Load RC register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDRC
Rm
Rm[11:0] → RC (SR[27:16]),
1 → RE[0]
0100mmmm00110100
LDRC
#imm
0 → RC (SR[27:24])
imm → RC (SR[23:16])
1 → RE[0]
10001010iiiiiiii
2
2


Description: This instruction sets the repeat number to RC bits in SR register. If the operand is
register, the lower 12-bit of the register is set to the RC. If the operand is immediate number, the
8-bit immediate data is set to the RC and the upper 4-bit is filled with zeros. And the repeat
control flag is set to RF1 and RF0 bit in SR register. After LDRC instruction is executed, the LSB
of RE register is set to 1, and the next instructions are targeted as the extended repeat. For details,
see 6.3.2 Extended Repeat control Instructions.
Note: LDRC instruction has some restrictions. Refer to 6.3.2 Extended Repeat control Instructions
for more information.
Rev. 1.50, 10/04, page 445 of 610
Operation:
LDRC(long m) /* LDRC Rm*/
{
 long temp;
 temp = (R[m] & 0x00000FFF)<<16;
 SR &= 0xF000FFFF;
 SR |= temp;
 RF1 = Repeat_Control_Flag1;
 RF0 = Repeat_Control_Flag0;
 PC += 2;
 RE[0] = 1;
}
LDRCI(long i) /* LDRC #imm*/
{
 long temp;
 temp = (R[m] & 0x000000FF)<<16;
 SR &= 0xF000FFFF;
 SR |= temp;
 RF1 = Repeat_Control_Flag1;
 RF0 = Repeat_Control_Flag0;
 PC += 2;
 RE[0] = 1;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 446 of 610
11.2.7 LDRE (Load Effective Address to RE Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDRE @(disp*,PC) disp × 2 + PC → RE 10001110dddddddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (x1, x2, or x4) as
the displacement (disp).
Description: Stores the effective address of the source operand in the repeat end register RE. The
effective address is an address specified by PC + displacement. The PC is the address four bytes
after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the
relative interval from the branch destination is –256 to +254 bytes.
Note: The effective address value designated for the RE reregister is different from the actual
repeat end address. Refer to table 6.5, RS and RE Setting Rule for the Convertion Repeat Control
in section 6, DSP Unit, for more information. When this instruction is arranged immediately after
the delayed branch instruction, PC becomes the "first address +2" of the branch destination.
If this instruction is executed in a delay slot, a slot illegal instruction exception occurs. And there
are some restrictions to use this instruction in a repeat loop. Refer to 6.3.1 DSP Convertion Repeat
Control Instructions and 6.3.2 Extended Repeat Control Instructions for more information.
Operation:
LDRE(long d) /* LDRE @(disp, PC) */
{
 long disp;
 if ((d&0x80)==0) disp = (0x000000FF & (long)d);
 else disp = (0xFFFFFF00 | (long)d);
 RE = PC + (disp<<1);
 PC += 2;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 447 of 610
11.2.8 LDS (Load to DSP System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDS Rm,DSR Rm → DSR 0100mmmm01101010 1 —
LDS Rm,A0 Rm → A0 0100mmmm01111010 1 —
LDS Rm,X0 Rm → X0 0100mmmm10001010 1 —
LDS Rm,X1 Rm → X1 0100mmmm10011010 1 —
LDS Rm,Y0 Rm → Y0 0100mmmm10101010 1 —
LDS Rm,Y1 Rm → Y1 0100mmmm10111010 1 —
LDS.L @Rm+,DSR (Rm) → DSR, Rm + 4 → Rm 0100mmmm01100110 1 —
LDS.L @Rm+,A0 (Rm) → A0, Rm + 4 → Rm 0100mmmm01110110 1 —
LDS.L @Rm+,X0 (Rm) → X0,Rm + 4 → Rm 0100nnnn10000110 1 —
LDS.L @Rm+,X1 (Rm) → X1,Rm + 4 → Rm 0100nnnn10010110 1 —
LDS.L @Rm+,Y0 (Rm) → Y0,Rm + 4 → Rm 0100nnnn10100110 1 —
LDS.L @Rm+,Y1 (Rm) → Y1,Rm + 4 → Rm 0100nnnn10110110 1 —
Description: Stores the source operand into the DSP system register DSR, and the DSP data
registers A0, X0, X1, Y0, and Y1.
Note: None
Operation:
LDSDSR(long m) /* LDS Rm,DSR */
{
 DSR = R[m] & 0x0000000F;
 PC += 2;
}
LDSA0(long m) /* LDS Rm,A0 */
{
 A0 = R[m];
 if((A0&0x80000000) == 0) A0G = 0x00;
 else A0G = 0xFF;
 PC += 2;
}
Rev. 1.50, 10/04, page 448 of 610
LDSX0(long m) /* LDS Rm,X0 */
{
 X0 = R[m];
 PC += 2;
}
LDSX1(long m) /* LDS Rm,X1 */
{
 X1 = R[m];
 PC += 2;
}
LDSY0(long m) /* LDS Rm,Y0 */
{
 Y0 = R[m];
 PC += 2;
}
LDSY1(long m) /* LDS Rm,Y1 */
{
 Y1 = R[m];
 PC += 2;
}
LDSMDSR(long m) /* LDS.L @Rm+,DSR */
{
 DSR = Read_Long(R[m])&0x0000000F;
 R[m] += 4;
 PC += 2;
}
Rev. 1.50, 10/04, page 449 of 610
LDSMA0(long m) /* LDS.L @Rm+,A0 */
{
 A0 = Read_Long(R[m]);
 if ((A0&0x80000000) == 0) A0G = 0x00;
 else A0G = 0xFF;
 R[m] += 4;
 PC += 2;
}
LDSMX0(long m) /* LDS.L @Rm+,X0 */
{
 X0 = Read_Long (R[m]);
 R[m] += 4;
 PC += 2;
}
LDSMX1(long m) /* LDS.L @Rm+,X1 */
{
 X1 = Read_Long (R[m]);
 R[m] += 4;
 PC += 2;
}
LDSMY0(long m) /* LDS.L @Rm+,Y0 */
{
 Y0 = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
}
LDSMY1(long m) /* LDS.L @Rm+,Y1 */
{
 Y1 = Read_Long(R[m]);
 R[m] += 4;
 PC += 2;
}
Rev. 1.50, 10/04, page 450 of 610
Examples:
LDS R0,PR ;Before execution R0 = H'12345678, PR = H'00000000
 ;After execution PR = H'12345678
LDS.L @R15+,MACL ;Before execution R15 = H'10000000
 ;After execution R15 = H'10000004, MACL = (H'10000000)
Possible Exceptions:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Rev. 1.50, 10/04, page 451 of 610
11.2.9 LDRS (Load Effective Address to RS Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDRS @(disp*,PC) disp × 2 + PC → RS 10001100dddddddd 1 —
Note: * The assembler of Renesas Technology uses the value after scaling (x1,x2, or x4) as
the displacement (disp).
Description: Stores the effective address of the source operand in the repeat start register RS. The
effective address is an address specified by PC + displacement. The PC is the address four bytes
after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the
relative interval from the branch destination is –256 to +254 bytes.
Note: When the instructions of the repeat (loop) program are below 3, the effective address value
designated for the RS register is different from the actual repeat start address. Refer to Table 6.5,
RS and RE setting rule for the convertion repeat control, for more information. If this instruction
is arranged immediately after the delayed branch instruction, the PC becomes "the first address
+2" of the branch destination.
If this instruction is executed in a delay slot, a slot illegal instruction exception occurs. And there
are some restrictions to use this instruction in a repeat loop. Refer to 6.3.1 DSP Conventional
Repeat Control Instructions and 6.3.2 Extended Repeat Control Instructions for more information.
Operation:
LDRS(long d) /* LDRS @(disp, PC) */
{
 long disp;
 if ((d&0x80)==0) disp = (0x000000FF & (long)d);
 else disp = (0xFFFFFF00 | (long)d);
 RS = PC + (disp<<1);
 PC += 2;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 452 of 610
11.2.10 SETDMX (Set DMX): System Control Instruction
Format Operation Instruction Code Cycle T Bit
SETDMX 1 → DMX (SR[10])
0 → DMY (SR[11])
0000000010011000 1 
Description: This instruction enables the X pointer modulo addressing mode by setting the DMX
bit and resetting the DMY bit of the SR register.
Note: When SR.DSP = 0, general illegal instruction exception occurs if SETDMX is executed not
in a delay slot, and slot illegal instruction occurs if SETDMX is executed in a delay slot.
Operation:
SETDMX( ) /* SETDMX */
{
 SR.DMX = 1;
 SR.DMY = 0;
 PC += 2;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 453 of 610
11.2.11 SETDMY (Set DMY): System Control Instruction
Format Operation Instruction Code Cycle T Bit
SETDMX 0 → DMX (SR[10])
1 → DMY (SR[11])
0000000011001000 1 
Description: This instruction enables the Y pointer modulo addressing mode by setting the DMY
bit and resetting the DMX bit of the SR register.
Note: When SR.DSP = 0, general illegal instruction exception occurs if SETDMY is executed not
in a delay slot, and slot illegal instruction occurs if SETDMY is executed in a delay slot.
Operation:
SETDMY( ) /* SETDMY */
{
 SR.DMX = 0;
 SR.DMY = 1;
 PC += 2;
}
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 454 of 610
11.2.12 SETRC (Set Repeat Count to RC): System Control Instruction
Format Operation Instruction Code Cycle T Bit
SETRC Rm Rm[11:0] → RC (SR[27:16]) 0100mmmm00010100 2 —
SETRC #imm imm → RC (SR[23:16]),
0 → RC (SR[27:24])
10000010iiiiiiii 2 —
Description: Sets the repeat count to the SR register's RC counter. When the operand is a register,
the bottom 12 bits are used as the repeat count. When the operand is an immediate data value, 8
bits are used as the repeat count. At this time, the upper 4 bits are filled with 0s. Set repeat control
flags to RF1, RF0 bits of the SR register. Use of the SETRC instruction is subject to any
limitations. Refer to section 6.3.1, DSP Conventional Repeat Control Instruction, for more
information.
Note: None
Operation:
SETRC(long m) /* SETRC Rm */
{
 long temp;
 temp = (R[m] & 0x00000FFF)<<16;
 SR &= 0xF000FFFF;
 SR |= temp;
 RF1 = Repeat_Control_Flag1;
 RF0 = Repeat_Control_Flag0;
 PC += 2;
}
Rev. 1.50, 10/04, page 455 of 610
SETRCI(long i) /* SETRC #imm */
{
 long temp;
 temp = ((long)i & 0x000000FF) << 16;
 SR &= 0xF000FFFF;
 SR |= temp;
 RF1 = Repeat_Control_Flag1;
 RF0 = Repeat_Control_Flag0;
 PC += 2;
}
SETRC #imm
7 0
SETRC Rm
imm
SR
8 bits
31 12 11 0
Rm
SR
1 ≤ imm ≤ 255 1 ≤ Rm [11:0] ≤ 4095
12 bits
31 27 23 16 15 0
0 8 bits 12 bits
31 27 16 15 0
Repeat control flag Repeat control flag
3 2 3 2
Possible Exceptions:
• General illegal instruction exception
• Slot illegal instruction exception
Rev. 1.50, 10/04, page 456 of 610
11.2.13 STC (Store Control Register): System Control Instruction (Some of these
instructions are usable as privileged instructions.Privileged Only)
Format Operation Instruction Code Cycle T Bit
STC SR,Rn SR → Rn 0000nnnn00000010 1 —
STC MOD,Rn MOD → Rn 0000nnnn01010010 1 —
STC RE,Rn RE → Rn 0000nnnn01110010 1 —
STC RS,Rn RS → Rn 0000nnnn01100010 1 —
STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 1 —
STC.L MOD,@-Rn Rn – 4 → Rn, MOD → (Rn) 0100nnnn01010011 1 —
STC.L RE,@-Rn Rn – 4 → Rn, RE → (Rn) 0100nnnn01110011 1 —
STC.L RS,@-Rn Rn – 4 → Rn, RS → (Rn) 0100nnnn01100011 1 —
Description: Stores data from control registers SR, MOD, RE and RS to a specified destination.
Notes: When the DSP bit of the SR register is clear (0), STC SR,Rn and STC.L SR,@Rn− are
privileged instructions. When the DSP bit is set (1), the instructions are not privileged, so all bits
are readable. The other six instructions are only executable in user mode.
Operation:
STCSR(long n) /*STC SR,Rn */
{
 R[n] = SR;
 PC += 2;
}
STCMOD(long n) /* STC MOD,Rn */
{
 R[n] = MOD
 PC += 2;
}
STCRE(long n) /* STC RE, Rn */
{
 R[n] = RE;
 PC += 2;
}
Rev. 1.50, 10/04, page 457 of 610
STCRS(long n) /* STC RS,Rn */
{
 R[n] = RS;
 PC += 2;
}
STCMSR(long n) /* STC.L SR,@-Rn */
{
 R[n] -= 4;
 Write_Long (R[n],SR);
 PC += 2;
}
STCMMOD(long n) /* STC.L MOD,@-Rn */
{
 R[n] -= 4;
 Write_Long (R[n],MOD);
 PC += 2;
}
STCMRE(long n) /* STC.L RE,@-Rn */
{
 R[n] -= 4;
 Write_Long (R[n],RE);
 PC += 2;
}
STCMRS(long n) /* STC.L RS, @-Rn */
{
 R[n] -= 4;
 Write_Long (R[n],RS);
 PC += 2;
}
Rev. 1.50, 10/04, page 458 of 610
Examples:
STC SR,R0 ;Before execution R0 = H'FFFFFFFF, SR = H'00000000
 ;After execution R0 = H'00000000
STC.L GBR,@-R15 ;Before execution R15 = H'10000004, GBR = H'12345678
 ;After execution R15 = H'10000000, (R15) = H'12345678
Possible Exceptions:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error
Rev. 1.50, 10/04, page 459 of 610
11.2.14 STS (Store from DSP System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
STS DSR,Rn DSR → Rn 0000nnnn01101010 1 —
STS A0,Rn A0 → Rn 0000nnnn01111010 1 —
STS X0,Rn X0 → Rn 0000nnnn10001010 1 —
STS X1,Rn X1 → Rn 0000nnnn10011010 1 —
STS Y0,Rn Y0 → Rn 0000nnnn10101010 1 —
STS Y1,Rn Y1 → Rn 0000nnnn10111010 1 —
STS.L DSR,@–Rn Rn – 4 → Rn, DSR → (Rn) 0100nnnn01100010 1 —
STS.L A0,@–Rn Rn – 4 → Rn, A0 → (Rn) 0100nnnn01110010 1 —
STS.L X0,@-Rn Rn – 4 → Rn,X0 → (Rn) 0100nnnn10000010 1 —
STS.L X1,@-Rn Rn – 4 → Rn,X1 → (Rn) 0100nnnn10010010 1 —
STS.L Y0,@-Rn Rn – 4 → Rn,Y0 → (Rn) 0100nnnn10100010 1 —
STS.L Y1,@-Rn Rn – 4 → Rn,Y1 → (Rn) 0100nnnn10110010 1 —
Description: Stores DSP system register DSR and DSP data registers A0, X0, X1, Y0, and Y1
data into a specified destination.
Note: None
Operation:
STSDSR (long n) /* STS DSR,Rn */
{
 R[n] = DSR;
 PC += 2;
}
STSA0 (long n) /* STS A0,Rn */
{
 R[n] = A0;
 PC += 2;
}
Rev. 1.50, 10/04, page 460 of 610
STSX0 (long n) /* STS X0,Rn */
{
 R[n] = X0;
 PC += 2;
}
STSX1(long n) /* STS X1,Rn */
{
 R[n] = X1;
 PC += 2;
}
STSY0(long n) /* STS Y0,Rn */
{
 R[n] = Y0;
 PC += 2;
}
STSY1(long n) /* STS Y1,Rn */
{
 R[n] = Y1;
 PC += 2;
}
STSMDSR(long n) /* STS.L DSR,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],DSR);
 PC += 2;
}
Rev. 1.50, 10/04, page 461 of 610
STSMA0(long n) /* STS.L A0,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],A0);
 PC += 2;
}
STSMX0(long n) /* STS.L X0,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],X0);
 PC += 2;
}
STSMX1(long n) /* STS.L X1,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],X1);
 PC += 2;
}
STSMY0(long n) /* STS.L Y0,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],Y0);
 PC += 2;
}
STSMY1(long n) /* STS.L Y1,@-Rn */
{
 R[n] -= 4;
 Write_Long(R[n],Y1);
 PC += 2;
}