#ifndef INSTRUCTIONS_H
#define INSTRUCTIONS_H

enum INSTRUCTIONS{
    //Data Transfer Instructions
    MOV_R_R,
    MOV_B_R,
    MOVA_PC_R0,
    MOVW_PC_R,
    MOVL_PC_R,
    MOVB_aR_R,
    MOVW_aR_R,
    MOVB_R_aR,
    MOVW_R_aR,
    MOVL_R_aR,
    MOVB_aRp_R,
    MOVW_aRp_R,
    MOVL_aRp_R,
    MOVB_R_amR,
    MOVW_R_amR,
    MOVL_R_amR,
    MOVB_PCR_R0,
    MOVW_PCR_R0,
    MOVL_PCR_R,
    MOVB_R0_PCR,
    MOVW_R0_PCR,
    MOVL_R_PCR,
    MOVB_R0R_R,
    MOVW_R0R_R,
    MOVL_R0R_R,
    MOVB_R_R0R,
    MOVW_R_R0R,
    MOVL_R_R0R,
    MOVB_PCGBR_R0,
    MOVW_PCGBR_R0,
    MOVL_PCGBR_R0,
    MOVB_R0_PCGBR,
    MOVW_R0_PCGBR,
    MOVL_R0_PCGBR,
    MOVCOL_R0_aR,
    MOVLIL_aR_R0,
    MOVUAL_aR_R0,
    MOVUAL_aRp_R0,
    MOVT_R,
    SWAPB_R_R,
    SWAPW_R_R,
    XTRCT_R_R,

    //Arithmetic Operation Instructions
    ADD_R_R,
    ADD_B_R,
    ADDC_R_R,
    ADDV_R_R,
    CMPEQ_B_R0,
    CMPEQ_R_R,
    CMPHS_R_R,
    CMPGE_R_R,
    CMPHI_R_R,
    CMPGT_R_R,
    CMPPL_R,
    CMPPZ_R,
    CMPSTR_R_R,
    DIV0S_R_R,
    DIV0U,
    DIV1_R_R,
    DMULSL_R_R,
    DMULUL_R_R,
    DT_R,
    EXTSB_R_R,
    EXTSW_R_R,
    EXTUB_R_R,
    EXTUW_R_R,
    MACL_aRp_aRp,
    MACW_aRp_aRp,
    MULL_R_R,
    MULSW_R_R,
    MULUW_R_R,
    NEG_R_R,
    NEGC_R_R,
    SUB_R_R,
    SUBC_R_R,
    SUBV_R_R,

    //Logic Operation Instructions
    AND_R_R,
    AND_B_R,
    ANDB_B_R0GBR,
    NOT_R_R,
    OR_R_R,
    OR_B_R,
    ORB_B_R0GBR,
    TASB_aR,
    TST_R_R,
    TST_B_R,
    TSTB_B_R0GBR,
    XOR_R_R,
    XOR_B_R,
    XORB_B_R0GBR

};

#endif