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inital commit

This commit is contained in:
IniKiwi 2022-07-05 19:20:34 +02:00
commit 01e3ae8541
21 changed files with 1662 additions and 0 deletions
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8
.gitignore vendored Normal file
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/build/.cmake
/build/CMakeFiles
/build/*.cmake
/build/CMakeCache.txt
/build/nemu
/.vscode
/*.txt
Makefile

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build/RIEN.G1A Normal file
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build/dissasembler.elf Executable file
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build/gravityd.g1a Normal file
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854
build/output.txt Normal file
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000000 aaac bra h'-aa8 ;@(h'fffff55c)
000002 bdaf bsr h'-4a2 ;@(h'fffffb64)
000004 9088 mov.w @(h'110,pc), r0 ;@(h'118)
000006 9a8d mov.w @(h'11a,pc), r10 ;@(h'124)
000008 0cff mac.l @r15+, @r12+
00000a efff mov #h'ffffffff, r15
00000c efff mov #h'ffffffff, r15
00000e 12fe mov.l r15, @(h'38,r2)
000010 ffff
000012 f953
000014 9b00 mov.w @(h'0,pc), r11 ;@(h'18)
000016 a262 bra h'4c4 ;@(h'4de)
000018 0000
00001a 0000
00001c 0000
00001e 0000
000020 4052
000022 4945
000024 4e00 shll r14
000026 0000
000028 0000
00002a 0000
00002c 0000
00002e 0000
000030 3031
000032 2e30 mov.b r3, @r14
000034 302e addc r2, r0
000036 3030 cmp/eq r3, r0
000038 3030 cmp/eq r3, r0
00003a 0000
00003c 3230 cmp/eq r3, r2
00003e 3232 cmp/hs r3, r2
000040 2e30 mov.b r3, @r14
000042 3730 cmp/eq r3, r7
000044 332e addc r2, r3
000046 3132 cmp/hs r3, r1
000048 3035 dmulu.l r3, r0
00004a 0000
00004c 7008
00004e 0004 mov.b r0, @(r0,r0)
000050 4808 shll2 r8
000052 0004 mov.b r0, @(r0,r0)
000054 44c8
000056 49c4
000058 452e ldc r5, vbr
00005a 4a44
00005c 45e9
00005e 4a44
000060 4909 shlr2 r9
000062 49c4
000064 70ee add #h'ee, r0
000066 3844 div1 r4, r8
000068 0000
00006a 0244 mov.b r4, @(r0,r2)
00006c 07df mac.l @r13+, @r7+
00006e 0184 mov.b r8, @(r0,r1)
000070 0451
000072 0004 mov.b r0, @(r0,r0)
000074 3f57 cmp/gt r5, r15
000076 e004 mov #h'4, r0
000078 2555 mov.w r5, @-r5
00007a 21fc cmp/str r15, r1
00007c 27df muls.w r13, r7
00007e 21fc cmp/str r15, r1
000080 2104 mov.b r0, @-r1
000082 21fc cmp/str r15, r1
000084 2104 mov.b r0, @-r1
000086 21fc cmp/str r15, r1
000088 3f07 cmp/gt r0, r15
00008a e1fc mov #h'fffffffc, r1
00008c 0000
00008e 01fc mov.b @(r0,r15), r1
000090 7fff add #h'ff, r15
000092 fffc
000094 0000
000096 0000
000098 0000
00009a 0000
00009c 0000
00009e 0000
0000a0 0000
0000a2 0000
0000a4 0000
0000a6 0000
0000a8 0000
0000aa 0000
0000ac 0000
0000ae 0000
0000b0 0000
0000b2 0000
0000b4 0000
0000b6 0000
0000b8 0000
0000ba 0000
0000bc 0000
0000be 0000
0000c0 0000
0000c2 0000
0000c4 0000
0000c6 0000
0000c8 0000
0000ca 0000
0000cc 0000
0000ce 0000
0000d0 0000
0000d2 0000
0000d4 0000
0000d6 0000
0000d8 0000
0000da 0000
0000dc 0000
0000de 0000
0000e0 0000
0000e2 0000
0000e4 0000
0000e6 0000
0000e8 0000
0000ea 0000
0000ec 0000
0000ee 0000
0000f0 0000
0000f2 0000
0000f4 0000
0000f6 0000
0000f8 0000
0000fa 0000
0000fc 0000
0000fe 0000
000100 0000
000102 0000
000104 0000
000106 0000
000108 0000
00010a 0000
00010c 0000
00010e 0000
000110 0000
000112 0000
000114 0000
000116 0000
000118 0000
00011a 0000
00011c 0000
00011e 0000
000120 0000
000122 0000
000124 0000
000126 0000
000128 0000
00012a 0000
00012c 0000
00012e 0000
000130 0000
000132 0000
000134 0000
000136 0000
000138 0000
00013a 0000
00013c 0000
00013e 0000
000140 0000
000142 0000
000144 0000
000146 0000
000148 0000
00014a 0000
00014c 0000
00014e 0000
000150 0000
000152 0000
000154 0000
000156 0000
000158 0000
00015a 0000
00015c 0000
00015e 0000
000160 0000
000162 0000
000164 0000
000166 0000
000168 0000
00016a 0000
00016c 0000
00016e 0000
000170 0000
000172 0000
000174 0000
000176 0000
000178 0000
00017a 0000
00017c 0000
00017e 0000
000180 0000
000182 0000
000184 0000
000186 0000
000188 0000
00018a 0000
00018c 0000
00018e 0000
000190 0000
000192 0000
000194 0000
000196 0000
000198 0000
00019a 0000
00019c 0000
00019e 0000
0001a0 0000
0001a2 0000
0001a4 0000
0001a6 0000
0001a8 0000
0001aa 0000
0001ac 0000
0001ae 0000
0001b0 0000
0001b2 0000
0001b4 0000
0001b6 0000
0001b8 0000
0001ba 0000
0001bc 0000
0001be 0000
0001c0 0000
0001c2 0000
0001c4 0000
0001c6 0000
0001c8 0000
0001ca 0000
0001cc 0000
0001ce 0000
0001d0 0000
0001d2 0000
0001d4 7269 add #h'69, r2
0001d6 656e exts.b r6, r5
0001d8 0000
0001da 0000
0001dc 0000
0001de 0000
0001e0 0000
0001e2 0000
0001e4 0000
0001e6 0000
0001e8 0000
0001ea 0000
0001ec 0000
0001ee 0000
0001f0 0000
0001f2 06ac mov.b @(r0,r10), r6
0001f4 0000
0001f6 0000
0001f8 0000
0001fa 0000
0001fc 0000
0001fe 0000
000200 d301 mov.l @(h'4,pc), r3 ;@(h'208)
000202 432b jmp @r3
000204 0009 nop
000206 0000
000208 0030
00020a 02fe mov.l @(r0,r15), r2
00020c d30c mov.l @(h'30,pc), r3 ;@(h'240)
00020e 7ffc add #h'fc, r15
000210 430b jsr @r3
000212 0009 nop
000214 d20b mov.l @(h'2c,pc), r2 ;@(h'244)
000216 e504 mov #h'4, r5
000218 420b jsr @r2
00021a e401 mov #h'1, r4
00021c d40a mov.l @(h'28,pc), r4 ;@(h'248)
00021e d30b mov.l @(h'2c,pc), r3 ;@(h'24c)
000220 430b jsr @r3
000222 0009 nop
000224 d207 mov.l @(h'1c,pc), r2 ;@(h'244)
000226 e505 mov #h'5, r5
000228 420b jsr @r2
00022a e401 mov #h'1, r4
00022c d408 mov.l @(h'20,pc), r4 ;@(h'250)
00022e d307 mov.l @(h'1c,pc), r3 ;@(h'24c)
000230 430b jsr @r3
000232 0009 nop
000234 de07 mov.l @(h'1c,pc), r14 ;@(h'254)
000236 4e0b jsr @r14
000238 64f3 mov r15, r4
00023a affc bra h'-8 ;@(h'236)
00023c 0009 nop
00023e 0000
000240 0030
000242 0384 mov.b r8, @(r0,r3)
000244 0030
000246 0430
000248 0030
00024a 0670
00024c 0030
00024e 0404 mov.b r0, @(r0,r4)
000250 0030
000252 0684 mov.b r8, @(r0,r6)
000254 0030
000256 03d4 mov.b r13, @(r0,r3)
000258 000b rts
00025a 0009 nop
00025c d333 mov.l @(h'cc,pc), r3 ;@(h'32c)
00025e 000b rts
000260 2342 mov.l r4, @r3
000262 2fe6 mov.l r14, @-r15
000264 2fd6 mov.l r13, @-r15
000266 2fc6 mov.l r12, @-r15
000268 4f22 sts.l pr, @-r15
00026a d230 mov.l @(h'c0,pc), r2 ;@(h'32c)
00026c 6e22 mov.l @r2, r14
00026e 2ee8 tst r14, r14
000270 8901 bt h'2 ;@(h'276)
000272 4e0b jsr @r14
000274 0009 nop
000276 de2e mov.l @(h'b8,pc), r14 ;@(h'330)
000278 4e0b jsr @r14
00027a e406 mov #h'6, r4
00027c 4e0b jsr @r14
00027e e407 mov #h'7, r4
000280 4e0b jsr @r14
000282 e408 mov #h'8, r4
000284 4e0b jsr @r14
000286 e409 mov #h'9, r4
000288 4e0b jsr @r14
00028a e40a mov #h'a, r4
00028c dc29 mov.l @(h'a4,pc), r12 ;@(h'334)
00028e ee04 mov #h'4, r14
000290 ed00 mov #h'0, r13
000292 4c0b jsr @r12
000294 64d3 mov r13, r4
000296 7d01
000298 3de3 cmp/ge r14, r13
00029a 8bfa bf h'-c ;@(h'292)
00029c dc26 mov.l @(h'98,pc), r12 ;@(h'338)
00029e ed00 mov #h'0, r13
0002a0 4c0b jsr @r12
0002a2 64d3 mov r13, r4
0002a4 7d01
0002a6 3de3 cmp/ge r14, r13
0002a8 8bfa bf h'-c ;@(h'2a0)
0002aa 4f26 lds.l @r15+, pr
0002ac d223 mov.l @(h'8c,pc), r2 ;@(h'33c)
0002ae 6cf6 mov.l @r15+, r12
0002b0 6df6 mov.l @r15+, r13
0002b2 422b jmp @r2
0002b4 6ef6 mov.l @r15+, r14
0002b6 4f22 sts.l pr, @-r15
0002b8 d521 mov.l @(h'84,pc), r5 ;@(h'340)
0002ba d422 mov.l @(h'88,pc), r4 ;@(h'344)
0002bc d322 mov.l @(h'88,pc), r3 ;@(h'348)
0002be 430b jsr @r3
0002c0 e66c mov #h'6c, r6
0002c2 e500 mov #h'0, r5
0002c4 d721 mov.l @(h'84,pc), r7 ;@(h'34c)
0002c6 d622 mov.l @(h'88,pc), r6 ;@(h'350)
0002c8 a002 bra h'4 ;@(h'2d0)
0002ca 6472 mov.l @r7, r4
0002cc 2452 mov.l r5, @r4
0002ce 7404
0002d0 6362 mov.l @r6, r3
0002d2 3432 cmp/hs r3, r4
0002d4 8bfa bf h'-c ;@(h'2cc)
0002d6 d61f mov.l @(h'7c,pc), r6 ;@(h'354)
0002d8 d31f mov.l @(h'7c,pc), r3 ;@(h'358)
0002da 6432 mov.l @r3, r4
0002dc d21f mov.l @(h'7c,pc), r2 ;@(h'35c)
0002de a003 bra h'6 ;@(h'2e8)
0002e0 6522 mov.l @r2, r5
0002e2 6356 mov.l @r5+, r3
0002e4 2432 mov.l r3, @r4
0002e6 7404
0002e8 6262 mov.l @r6, r2
0002ea 3422 cmp/hs r2, r4
0002ec 8bf9 bf h'-e ;@(h'2e2)
0002ee 6372 mov.l @r7, r3
0002f0 6162 mov.l @r6, r1
0002f2 3138 sub r3, r1
0002f4 d31a mov.l @(h'68,pc), r3 ;@(h'360)
0002f6 7104
0002f8 4f26 lds.l @r15+, pr
0002fa 000b rts
0002fc 2312 mov.l r1, @r3
0002fe 6053 mov r5, r0
000300 4f22 sts.l pr, @-r15
000302 7ff8 add #h'f8, r15
000304 2f42 mov.l r4, @r15
000306 bfd6 bsr h'-54 ;@(h'2b6)
000308 81f2 mov.w r0, @(h'4,r15)
00030a e601 mov #h'1, r6
00030c d215 mov.l @(h'54,pc), r2 ;@(h'364)
00030e 6563 mov r6, r5
000310 420b jsr @r2
000312 e400 mov #h'0, r4
000314 d414 mov.l @(h'50,pc), r4 ;@(h'368)
000316 d315 mov.l @(h'54,pc), r3 ;@(h'36c)
000318 430b jsr @r3
00031a 0009 nop
00031c 85f2 mov.w @(h'4,r15), r0
00031e 6503 mov r0, r5
000320 64f2 mov.l @r15, r4
000322 655d extu.w r5, r5
000324 d312 mov.l @(h'48,pc), r3 ;@(h'370)
000326 7f08
000328 432b jmp @r3
00032a 4f26 lds.l @r15+, pr
00032c 0810
00032e 0008 clrt
000330 0030
000332 0374 mov.b r7, @(r0,r3)
000334 0030
000336 0394 mov.b r9, @(r0,r3)
000338 0030
00033a 03c4 mov.b r12, @(r0,r3)
00033c 0030
00033e 03a4 mov.b r10, @(r0,r3)
000340 8801 cmp/eq #h'1, r0
000342 e000 mov #h'0, r0
000344 0810
000346 2000 mov.b r0, @r0
000348 0030
00034a 03f4 mov.b r15, @(r0,r3)
00034c 0030
00034e 0694 mov.b r9, @(r0,r6)
000350 0030
000352 0698
000354 0030
000356 06a0
000358 0030
00035a 069c mov.b @(r0,r9), r6
00035c 0030
00035e 06a4 mov.b r10, @(r0,r6)
000360 0810
000362 0000
000364 0030
000366 03e4 mov.b r14, @(r0,r3)
000368 0030
00036a 0262
00036c 0030
00036e 03b4 mov.b r11, @(r0,r3)
000370 0030
000372 020c mov.b @(r0,r0), r2
000374 d201 mov.l @(h'4,pc), r2 ;@(h'37c)
000376 d002 mov.l @(h'8,pc), r0 ;@(h'380)
000378 422b jmp @r2
00037a 0009 nop
00037c 8001 mov.b r0, @(h'1,r0)
00037e 0070
000380 0000
000382 0119 div0u
000384 d201 mov.l @(h'4,pc), r2 ;@(h'38c)
000386 d002 mov.l @(h'8,pc), r0 ;@(h'390)
000388 422b jmp @r2
00038a 0009 nop
00038c 8001 mov.b r0, @(h'1,r0)
00038e 0070
000390 0000
000392 0144 mov.b r4, @(r0,r1)
000394 d201 mov.l @(h'4,pc), r2 ;@(h'39c)
000396 d002 mov.l @(h'8,pc), r0 ;@(h'3a0)
000398 422b jmp @r2
00039a 0009 nop
00039c 8001 mov.b r0, @(h'1,r0)
00039e 0070
0003a0 0000
0003a2 01e7 mul.l r14, r1
0003a4 d201 mov.l @(h'4,pc), r2 ;@(h'3ac)
0003a6 d002 mov.l @(h'8,pc), r0 ;@(h'3b0)
0003a8 422b jmp @r2
0003aa 0009 nop
0003ac 8001 mov.b r0, @(h'1,r0)
0003ae 0070
0003b0 0000
0003b2 0244 mov.b r4, @(r0,r2)
0003b4 d201 mov.l @(h'4,pc), r2 ;@(h'3bc)
0003b6 d002 mov.l @(h'8,pc), r0 ;@(h'3c0)
0003b8 422b jmp @r2
0003ba 0009 nop
0003bc 8001 mov.b r0, @(h'1,r0)
0003be 0070
0003c0 0000
0003c2 0494 mov.b r9, @(r0,r4)
0003c4 d201 mov.l @(h'4,pc), r2 ;@(h'3cc)
0003c6 d002 mov.l @(h'8,pc), r0 ;@(h'3d0)
0003c8 422b jmp @r2
0003ca 0009 nop
0003cc 8001 mov.b r0, @(h'1,r0)
0003ce 0070
0003d0 0000
0003d2 0218 sett
0003d4 d201 mov.l @(h'4,pc), r2 ;@(h'3dc)
0003d6 d002 mov.l @(h'8,pc), r0 ;@(h'3e0)
0003d8 422b jmp @r2
0003da 0009 nop
0003dc 8001 mov.b r0, @(h'1,r0)
0003de 0070
0003e0 0000
0003e2 090f mac.l @r0+, @r9+
0003e4 d201 mov.l @(h'4,pc), r2 ;@(h'3ec)
0003e6 d002 mov.l @(h'8,pc), r0 ;@(h'3f0)
0003e8 422b jmp @r2
0003ea 0009 nop
0003ec 8001 mov.b r0, @(h'1,r0)
0003ee 0070
0003f0 0000
0003f2 0013
0003f4 d201 mov.l @(h'4,pc), r2 ;@(h'3fc)
0003f6 d002 mov.l @(h'8,pc), r0 ;@(h'400)
0003f8 422b jmp @r2
0003fa 0009 nop
0003fc 8001 mov.b r0, @(h'1,r0)
0003fe 0070
000400 0000
000402 03fa
000404 d201 mov.l @(h'4,pc), r2 ;@(h'40c)
000406 d002 mov.l @(h'8,pc), r0 ;@(h'410)
000408 422b jmp @r2
00040a 0009 nop
00040c 8001 mov.b r0, @(h'1,r0)
00040e 0070
000410 0000
000412 0808 clrt
000414 4511 cmp/pz r5
000416 8b04 bf h'8 ;@(h'422)
000418 e23b mov #h'3b, r2
00041a 3527 cmp/gt r2, r5
00041c 8901 bt h'2 ;@(h'422)
00041e 4411 cmp/pz r4
000420 8901 bt h'2 ;@(h'426)
000422 000b rts
000424 e000 mov #h'0, r0
000426 d32d mov.l @(h'b4,pc), r3 ;@(h'4dc)
000428 432b jmp @r3
00042a 0009 nop
00042c 000b rts
00042e 0009 nop
000430 4415 cmp/pl r4
000432 8d02 bt/s h'4 ;@(h'43a)
000434 e601 mov #h'1, r6
000436 a004 bra h'8 ;@(h'442)
000438 6463 mov r6, r4
00043a e715 mov #h'15, r7
00043c 3477 cmp/gt r7, r4
00043e 8b00 bf h'0 ;@(h'442)
000440 6473 mov r7, r4
000442 4515 cmp/pl r5
000444 8901 bt h'2 ;@(h'44a)
000446 a004 bra h'8 ;@(h'452)
000448 6563 mov r6, r5
00044a e608 mov #h'8, r6
00044c 3567 cmp/gt r6, r5
00044e 8b00 bf h'0 ;@(h'452)
000450 6563 mov r6, r5
000452 d323 mov.l @(h'8c,pc), r3 ;@(h'4e0)
000454 432b jmp @r3
000456 0009 nop
000458 2fe6 mov.l r14, @-r15
00045a 2fd6 mov.l r13, @-r15
00045c 2fc6 mov.l r12, @-r15
00045e 2fb6 mov.l r11, @-r15
000460 2fa6 mov.l r10, @-r15
000462 2f96 mov.l r9, @-r15
000464 2f86 mov.l r8, @-r15
000466 4f22 sts.l pr, @-r15
000468 7ff0 add #h'f0, r15
00046a 2f52 mov.l r5, @r15
00046c 5342 mov.l @(h'8,r4), r3
00046e 6242 mov.l @r4, r2
000470 3237 cmp/gt r3, r2
000472 8f03 bf/s h'6 ;@(h'47c)
000474 5243 mov.l @(h'c,r4), r2
000476 5542 mov.l @(h'8,r4), r5
000478 a002 bra h'4 ;@(h'480)
00047a 6642 mov.l @r4, r6
00047c 6542 mov.l @r4, r5
00047e 5642 mov.l @(h'8,r4), r6
000480 5341 mov.l @(h'4,r4), r3
000482 3327 cmp/gt r2, r3
000484 8b02 bf h'4 ;@(h'48c)
000486 5d43 mov.l @(h'c,r4), r13
000488 a002 bra h'4 ;@(h'490)
00048a 5841 mov.l @(h'4,r4), r8
00048c 5d41 mov.l @(h'4,r4), r13
00048e 5843 mov.l @(h'c,r4), r8
000490 4511 cmp/pz r5
000492 8b70 bf h'e0 ;@(h'576)
000494 9321 mov.w @(h'42,pc), r3 ;@(h'4da)
000496 3633 cmp/ge r3, r6
000498 896d bt h'da ;@(h'576)
00049a 4d11 cmp/pz r13
00049c 8b6b bf h'd6 ;@(h'576)
00049e e240 mov #h'40, r2
0004a0 3823 cmp/ge r2, r8
0004a2 8968 bt h'd0 ;@(h'576)
0004a4 d20f mov.l @(h'3c,pc), r2 ;@(h'4e4)
0004a6 e408 mov #h'8, r4
0004a8 6153 mov r5, r1
0004aa 420b jsr @r2
0004ac 6043 mov r4, r0
0004ae 6163 mov r6, r1
0004b0 d30c mov.l @(h'30,pc), r3 ;@(h'4e4)
0004b2 1f02 mov.l r0, @(h'8,r15)
0004b4 430b jsr @r3
0004b6 6043 mov r4, r0
0004b8 6c03 mov r0, r12
0004ba 6053 mov r5, r0
0004bc 4011 cmp/pz r0
0004be 8b01 bf h'2 ;@(h'4c4)
0004c0 a005 bra h'a ;@(h'4ce)
0004c2 c907 and #h'7, r0
0004c4 6007 not r0, r0
0004c6 7001
0004c8 c907 and #h'7, r0
0004ca 6007 not r0, r0
0004cc 7001
0004ce 2008 tst r0, r0
0004d0 db05 mov.l @(h'14,pc), r11 ;@(h'4e8)
0004d2 8f1f bf/s h'3e ;@(h'514)
0004d4 1f01 mov.l r0, @(h'4,r15)
0004d6 a019 bra h'32 ;@(h'50c)
0004d8 0009 nop
0004da 0080
0004dc 0030
0004de 0660
0004e0 0030
0004e2 0650
0004e4 0030
0004e6 058c mov.b @(r0,r8), r5
0004e8 0030
0004ea 0640
0004ec 5ef2 mov.l @(h'8,r15), r14
0004ee 3ec7 cmp/gt r12, r14
0004f0 8d0b bt/s h'16 ;@(h'50a)
0004f2 6ad3 mov r13, r10
0004f4 64e3 mov r14, r4
0004f6 4b0b jsr @r11
0004f8 65a3 mov r10, r5
0004fa 6403 mov r0, r4
0004fc 62f2 mov.l @r15, r2
0004fe 7e01
000500 7201
000502 3ec7 cmp/gt r12, r14
000504 2f22 mov.l r2, @r15
000506 8ff5 bf/s h'-16 ;@(h'4f4)
000508 2244 mov.b r4, @-r2
00050a 7d01
00050c 3d87 cmp/gt r8, r13
00050e 8bed bf h'-26 ;@(h'4ec)
000510 a031 bra h'62 ;@(h'576)
000512 0009 nop
000514 3658 sub r5, r6
000516 7608
000518 4611 cmp/pz r6
00051a 8900 bt h'0 ;@(h'51e)
00051c 7607
00051e 4621 shar r6
000520 53f2 mov.l @(h'8,r15), r3
000522 62c3 mov r12, r2
000524 4621 shar r6
000526 4621 shar r6
000528 3238 sub r3, r2
00052a 3627 cmp/gt r2, r6
00052c 8b00 bf h'0 ;@(h'530)
00052e 7c01
000530 53f1 mov.l @(h'4,r15), r3
000532 3438 sub r3, r4
000534 a01d bra h'3a ;@(h'572)
000536 1f43 mov.l r4, @(h'c,r15)
000538 5ef2 mov.l @(h'8,r15), r14
00053a 3ec3 cmp/ge r12, r14
00053c 8d18 bt/s h'30 ;@(h'570)
00053e 69d3 mov r13, r9
000540 64e3 mov r14, r4
000542 4b0b jsr @r11
000544 6593 mov r9, r5
000546 6a03 mov r0, r10
000548 64e3 mov r14, r4
00054a 7401
00054c 4b0b jsr @r11
00054e 6593 mov r9, r5
000550 62f2 mov.l @r15, r2
000552 61ac extu.b r10, r1
000554 6403 mov r0, r4
000556 7201
000558 2f22 mov.l r2, @r15
00055a 644c extu.b r4, r4
00055c 53f3 mov.l @(h'c,r15), r3
00055e 7e01
000560 633b neg r3, r3
000562 443d shld r3, r4
000564 53f1 mov.l @(h'4,r15), r3
000566 3ec3 cmp/ge r12, r14
000568 413d shld r3, r1
00056a 241b or r1, r4
00056c 8fe8 bf/s h'-30 ;@(h'540)
00056e 2244 mov.b r4, @-r2
000570 7d01
000572 3d87 cmp/gt r8, r13
000574 8be0 bf h'-40 ;@(h'538)
000576 7f10 add #h'10, r15
000578 4f26 lds.l @r15+, pr
00057a 68f6 mov.l @r15+, r8
00057c 69f6 mov.l @r15+, r9
00057e 6af6 mov.l @r15+, r10
000580 6bf6 mov.l @r15+, r11
000582 6cf6 mov.l @r15+, r12
000584 6df6 mov.l @r15+, r13
000586 000b rts
000588 6ef6 mov.l @r15+, r14
00058a 0000
00058c 2008 tst r0, r0
00058e 2f26 mov.l r2, @-r15
000590 894b bt h'96 ;@(h'62a)
000592 2f36 mov.l r3, @-r15
000594 e200 mov #h'0, r2
000596 2127 div0s r2, r1
000598 333a subc r3, r3
00059a 312a subc r2, r1
00059c 2307 div0s r0, r3
00059e 4124 rotcl r1
0005a0 3304 div1 r0, r3
0005a2 4124 rotcl r1
0005a4 3304 div1 r0, r3
0005a6 4124 rotcl r1
0005a8 3304 div1 r0, r3
0005aa 4124 rotcl r1
0005ac 3304 div1 r0, r3
0005ae 4124 rotcl r1
0005b0 3304 div1 r0, r3
0005b2 4124 rotcl r1
0005b4 3304 div1 r0, r3
0005b6 4124 rotcl r1
0005b8 3304 div1 r0, r3
0005ba 4124 rotcl r1
0005bc 3304 div1 r0, r3
0005be 4124 rotcl r1
0005c0 3304 div1 r0, r3
0005c2 4124 rotcl r1
0005c4 3304 div1 r0, r3
0005c6 4124 rotcl r1
0005c8 3304 div1 r0, r3
0005ca 4124 rotcl r1
0005cc 3304 div1 r0, r3
0005ce 4124 rotcl r1
0005d0 3304 div1 r0, r3
0005d2 4124 rotcl r1
0005d4 3304 div1 r0, r3
0005d6 4124 rotcl r1
0005d8 3304 div1 r0, r3
0005da 4124 rotcl r1
0005dc 3304 div1 r0, r3
0005de 4124 rotcl r1
0005e0 3304 div1 r0, r3
0005e2 4124 rotcl r1
0005e4 3304 div1 r0, r3
0005e6 4124 rotcl r1
0005e8 3304 div1 r0, r3
0005ea 4124 rotcl r1
0005ec 3304 div1 r0, r3
0005ee 4124 rotcl r1
0005f0 3304 div1 r0, r3
0005f2 4124 rotcl r1
0005f4 3304 div1 r0, r3
0005f6 4124 rotcl r1
0005f8 3304 div1 r0, r3
0005fa 4124 rotcl r1
0005fc 3304 div1 r0, r3
0005fe 4124 rotcl r1
000600 3304 div1 r0, r3
000602 4124 rotcl r1
000604 3304 div1 r0, r3
000606 4124 rotcl r1
000608 3304 div1 r0, r3
00060a 4124 rotcl r1
00060c 3304 div1 r0, r3
00060e 4124 rotcl r1
000610 3304 div1 r0, r3
000612 4124 rotcl r1
000614 3304 div1 r0, r3
000616 4124 rotcl r1
000618 3304 div1 r0, r3
00061a 4124 rotcl r1
00061c 3304 div1 r0, r3
00061e 4124 rotcl r1
000620 312e addc r2, r1
000622 6013 mov r1, r0
000624 63f6 mov.l @r15+, r3
000626 000b rts
000628 62f6 mov.l @r15+, r2
00062a d103 mov.l @(h'c,pc), r1 ;@(h'638)
00062c d203 mov.l @(h'c,pc), r2 ;@(h'63c)
00062e e000 mov #h'0, r0
000630 2122 mov.l r2, @r1
000632 000b rts
000634 62f6 mov.l @r15+, r2
000636 0009 nop
000638 0810
00063a 0004 mov.b r0, @(r0,r0)
00063c 0000
00063e 044e mov.l @(r0,r4), r4
000640 d201 mov.l @(h'4,pc), r2 ;@(h'648)
000642 d002 mov.l @(h'8,pc), r0 ;@(h'64c)
000644 422b jmp @r2
000646 0009 nop
000648 8001 mov.b r0, @(h'1,r0)
00064a 0070
00064c 0000
00064e 0026 mov.l r2, @(r0,r0)
000650 d201 mov.l @(h'4,pc), r2 ;@(h'658)
000652 d002 mov.l @(h'8,pc), r0 ;@(h'65c)
000654 422b jmp @r2
000656 0009 nop
000658 8001 mov.b r0, @(h'1,r0)
00065a 0070
00065c 0000
00065e 0807 mul.l r0, r8
000660 d201 mov.l @(h'4,pc), r2 ;@(h'668)
000662 d002 mov.l @(h'8,pc), r0 ;@(h'66c)
000664 422b jmp @r2
000666 0009 nop
000668 8001 mov.b r0, @(h'1,r0)
00066a 0070
00066c 0000
00066e 0c4f mac.l @r4+, @r12+
000670 5468 mov.l @(h'20,r6), r4
000672 6973 mov r7, r9
000674 2061 mov.w r6, @r0
000676 7070 add #h'70, r0
000678 6c69 swap.w r6, r12
00067a 6361 mov.w @r6, r3
00067c 7469 add #h'69, r4
00067e 6f6e exts.b r6, r15
000680 2069 and r6, r0
000682 7300
000684 2073
000686 616d extu.w r6, r1
000688 706c add #h'6c, r0
00068a 6520 mov.b @r2, r5
00068c 4164
00068e 642d extu.w r2, r4
000690 496e
000692 2e00 mov.b r0, @r14
000694 0810
000696 0004 mov.b r0, @(r0,r0)
000698 0810
00069a 0008 clrt
00069c 0810
00069e 0008 clrt
0006a0 0810
0006a2 000c mov.b @(r0,r0), r0
0006a4 0030
0006a6 06a8
0006a8 0000
0006aa 0000

236
src/cpu.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <cpu.h>
#include <log.h>
#include <instructions/instructions.h>
uint32_t decode(unsigned char a,unsigned char b,unsigned char c,unsigned char d)
{
return ((uint32_t)d << 24) | ((uint32_t)c << 16) | ((uint32_t)b << 8) | (uint32_t)a;
}
uint16_t decode16(unsigned char a,unsigned char b)
{
return ((uint16_t)b << 8) | (uint16_t)a;
}
int cpu_setup_addin(cpu_status_t* status,char* _file){
FILE * addin_file;
addin_file = fopen(_file, "rb");
if(addin_file == NULL){
return 1;
}
printf("file: %s\n",_file);
fseek(addin_file, 0L, SEEK_END);
status->program_size = ftell(addin_file) - 0x200L;
status->rom = malloc(status->program_size);
fseek(addin_file, 0x200L,SEEK_SET);
fread(status->rom, status->program_size, 1, addin_file);
fclose(addin_file);
printf("%d bytes allocated\n",status->program_size);
status->pc = 0x00300200;
for(int i=0; i<32768; i++){
status->ram[i] = 0x00;
}
}
int cpu_run(cpu_status_t* status){
}
uint32_t cpu_read32(cpu_status_t* status, uint32_t addr){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
uint32_t ret;
ret = decode(status->ram[addr-0x08100000+3], status->ram[addr-0x08100000+2], status->ram[addr-0x08100000+1], status->ram[addr-0x08100000]);
return ret;
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
uint32_t ret;
ret = decode(status->rom[addr-0x00300200+3], status->rom[addr-0x00300200+2], status->rom[addr-0x00300200+1], status->rom[addr-0x00300200]);
return ret;
}
else{
log_mem_read_error(status, addr);
return 0;
}
}
uint16_t cpu_read16(cpu_status_t* status, uint32_t addr){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
uint16_t ret;
//ret = (uint16_t)status->ram[addr-0x08100000];
memcpy(&ret,&status->ram[addr-0x08100000],2);
return ret;
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
uint16_t ret;
ret = status->rom[addr-0x00300200+1];
ret <<= 8;
ret |= status->rom[addr-0x00300200];
//memcpy(&ret,&status->ram[addr-0x00300000],1);
//ret = (uint16_t)status->rom[addr-0x00300000];
return ret;
}
else{
log_mem_read_error(status, addr);
return 0;
}
}
uint8_t cpu_read8(cpu_status_t* status, uint32_t addr){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
uint8_t ret;
ret = status->ram[addr-0x08100000];
return ret;
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
uint8_t ret;
ret = status->rom[addr-0x00300200];
return ret;
}
else{
log_mem_read_error(status, addr);
return 8;
}
}
void cpu_write32(cpu_status_t* status, uint32_t addr, uint32_t data){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
unsigned char bytes[4];
status->ram[addr-0x08100000] = (data >> 24) & 0xFF;
status->ram[addr-0x08100000+1] = (data >> 16) & 0xFF;
status->ram[addr-0x08100000+2] = (data >> 8) & 0xFF;
status->ram[addr-0x08100000+3] = data & 0xFF;
//memcpy(&status->ram[addr-0x08100000],&data, 4);
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
memcpy(&status->rom[addr-0x00300200], &addr, 4);
}
else{
log_mem_write_error(status, addr);
}
}
void cpu_write16(cpu_status_t* status, uint16_t addr, uint16_t data){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
memcpy(&status->ram[addr-0x08100000],&data, 2);
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
memcpy(&status->rom[addr-0x00300200], &addr, 2);
}
else{
log_mem_write_error(status, addr);
}
}
void cpu_write8(cpu_status_t* status, uint32_t addr, uint8_t data){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
status->ram[addr-0x08100000] = data;
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
status->rom[addr-0x00300200] = data;
}
else{
log_mem_write_error(status, addr);
}
}
int cpu_execute(cpu_status_t* status){
char nibble[4] = {
HI_NIBBLE(cpu_read8(status,status->pc)),
LO_NIBBLE(cpu_read8(status,status->pc)),
HI_NIBBLE(cpu_read8(status,status->pc+1)),
LO_NIBBLE(cpu_read8(status,status->pc+1))
};
printf("pc: %8x r0: %8x r1: %8x r2: %8x r3: %8x r4: %8x r5: %8x r6: %8x\n",
status->pc,
status->r[0],status->r[1],status->r[2],status->r[3],
status->r[4],status->r[5],status->r[6]
);
if(nibble[0] == 0b0110 && nibble[3] == 0b0011) instruction_mov_r_r(status);
else if(nibble[0] == 0b1110) instruction_mov_imm_r(status);
else if(nibble[0] == 0b1101) instruction_movl_disp_pc_r(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b0010) instruction_movl_ar_r(status);
else if(nibble[0] == 0b0010 && nibble[3] == 0b0010) instruction_movl_r_ar(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b0110) instruction_movl_arp_r(status);
else if(nibble[0] == 0b0010 && nibble[3] == 0b0110) instruction_movl_r_amr(status);
else if(nibble[0] == 0b0101) instruction_movl_disp_r_r(status);
else if(nibble[0] == 0b0001) instruction_movl_r_disp_r(status);
else if(nibble[0] == 0b0000 && nibble[3] == 0b1110) instruction_movl_r0_r_r(status);
else if(nibble[0] == 0b0000 && nibble[3] == 0b0110) instruction_movl_r_r0_r(status);
else if(nibble[0] == 0b1100 && nibble[1] == 0b0110) instruction_movl_disp_gbr_r0(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b0001) instruction_movw_r0_disp_r(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b0000) instruction_movb_ar_r(status);
else if(nibble[0] == 0b0010 && nibble[3] == 0b0000) instruction_movb_r_ar(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b0100) instruction_movb_arp_r(status);
else if(nibble[0] == 0b0010 && nibble[3] == 0b0100) instruction_movb_r_amr(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b0100) instruction_movb_disp_r_r0(status);
else if(nibble[0] == 0b0000 && nibble[3] == 0b1100) instruction_movb_r0_r_r(status);
else if(nibble[0] == 0b0000 && nibble[3] == 0b0100) instruction_movb_r_r0_r(status);
else if(nibble[0] == 0b1100 && nibble[1] == 0b0100) instruction_movb_disp_gbr_r0(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0100) instruction_roctl_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b0100) instruction_div1_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b1100) instruction_add_r_r(status);
else if(nibble[0] == 0b0111) instruction_add_imm_r(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0001) instruction_cmp_pz_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b0111) instruction_cmp_gt_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b0010) instruction_cmp_hs_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b1000) instruction_add_r_r(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b1011) instruction_jmp_r(status);
else if(nibble[0] == 0b1011) instruction_bsr_lbl(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b1011) instruction_jsr_ar(status);
else if(nibble[0] == 0b0000 && nibble[2] == 0b0000 && nibble[2] == 0b0000 && nibble[3] == 0b1011) instruction_rts(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b1011 ) instruction_bf_lbl(status);
else if(nibble[0] == 0b1010) instruction_bra_lbl(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b1001 ) instruction_bt_lbl(status);
else if(nibble[0] == 0b0000 && nibble[1] == 0b0000 && nibble[2] == 0b0000 && nibble[3] == 0b1001) instruction_nop(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b0010) instruction_stsl_mash_amr(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0010) instruction_stsl_macl_amr(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0010) instruction_stsl_pr_amr(status);
else if(nibble[0] == 0b0000 && nibble[1] == 0b0000 && nibble[2] == 0b0000 && nibble[3] == 0b1000) instruction_clrt(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0110) instruction_ldsl_arp_pr(status);
else{status->pc += 2; printf("\e[33munkdown opcode, skipping...\e[39m\n");return 1;}
return 0;
}
int cpu_run_from(cpu_status_t* status, uint32_t addr){
status->pc = addr;
int total_error = 0;
int total_executions = 0;
while (status->pc-0x00300200 < status->program_size){
if(cpu_execute(status)){
total_error++;
}
total_executions++;
/*if(total_executions > 500){
break;
}*/
}
printf("excution terminated with %d not found opcodes\n",total_error);
}

35
src/cpu.h Normal file
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#include <stdint.h>
#include <stdbool.h>
#pragma once
typedef struct{
uint32_t r[16];
uint32_t pc;
uint32_t pr;
uint32_t sr;
uint32_t mach;
uint32_t macl;
uint32_t gbr;
uint8_t* rom;
uint8_t ram[32768]; // 0x08100000
uint32_t program_size;
uint8_t t;
uint8_t q;
uint8_t m;
}cpu_status_t;
int cpu_setup_addin(cpu_status_t*, char*);
int cpu_execute(cpu_status_t*);
int cpu_run_from(cpu_status_t*, uint32_t);
uint32_t cpu_read32(cpu_status_t*, uint32_t);
uint16_t cpu_read16(cpu_status_t*, uint32_t);
uint8_t cpu_read8(cpu_status_t*, uint32_t);
void cpu_write32(cpu_status_t* status, uint32_t addr, uint32_t data);
void cpu_write16(cpu_status_t* status, uint16_t addr, uint16_t data);
void cpu_write8(cpu_status_t* status, uint32_t addr, uint8_t data);

55
src/instructions/instructions.h Normal file
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#include <cpu.h>
#pragma once
#define HI_NIBBLE(b) (((b) >> 4) & 0x0F)
#define LO_NIBBLE(b) ((b) & 0x0F)
void instruction_mov_r_r(cpu_status_t*);
void instruction_mov_imm_r(cpu_status_t*);
void instruction_movl_disp_pc_r(cpu_status_t*);
void instruction_movl_ar_r(cpu_status_t*);
void instruction_movl_r_ar(cpu_status_t*);
void instruction_movl_arp_r(cpu_status_t*);
void instruction_movl_r_amr(cpu_status_t*);
void instruction_movl_disp_r_r(cpu_status_t*);
void instruction_movl_r_disp_r(cpu_status_t*);
void instruction_movl_r0_r_r(cpu_status_t*);
void instruction_movl_r_r0_r(cpu_status_t*);
void instruction_movl_disp_gbr_r0(cpu_status_t*);
void instruction_movw_r0_disp_r(cpu_status_t* status);
void instruction_movb_ar_r(cpu_status_t* status);
void instruction_movb_r_ar(cpu_status_t* status);
void instruction_movb_arp_r(cpu_status_t* status);
void instruction_movb_r_amr(cpu_status_t* status);
void instruction_movb_disp_r_r0(cpu_status_t* status);
void instruction_movb_r0_r_r(cpu_status_t* status);
void instruction_movb_r_r0_r (cpu_status_t* status);
void instruction_movb_disp_gbr_r0(cpu_status_t* status);
void instruction_roctl_r(cpu_status_t* status);
void instruction_div1_r_r(cpu_status_t* status);
void instruction_add_r_r(cpu_status_t* status);
void instruction_add_imm_r(cpu_status_t* status);
void instruction_cmp_pz_r(cpu_status_t* status);
void instruction_cmp_gt_r_r(cpu_status_t* status);
void instruction_cmp_hs_r_r(cpu_status_t* status);
void instruction_sub_r_r(cpu_status_t* status);
void instruction_jmp_r(cpu_status_t* status);
void instruction_bsr_lbl(cpu_status_t* status);
void instruction_jsr_ar(cpu_status_t* status);
void instruction_rts(cpu_status_t* status);
void instruction_bf_lbl(cpu_status_t* status);
void instruction_bra_lbl(cpu_status_t* status);
void instruction_bt_lbl(cpu_status_t* status);
void instruction_nop(cpu_status_t* status);
void instruction_stsl_mash_amr(cpu_status_t* status);
void instruction_stsl_macl_amr (cpu_status_t* status);
void instruction_stsl_pr_amr(cpu_status_t* status);
void instruction_clrt(cpu_status_t* status);
void instruction_ldsl_arp_pr(cpu_status_t* status);

120
src/instructions/jmp.c Normal file
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#include <instructions/instructions.h>
#include <stdio.h>
#include <syscall.h>
void instruction_jmp_r(cpu_status_t* status){
unsigned int temp;
temp = status->pc;
status->pc += 2;
cpu_execute(status);
status->pc = temp;
if(status->r[LO_NIBBLE(cpu_read8(status,temp))] != 0x80010070){
status->pc = status->r[LO_NIBBLE(cpu_read8(status,temp))];
printf("\e[34mpc: %8x jump to %08x (r%02d)\e[39m\n", temp, status->r[LO_NIBBLE(cpu_read8(status,temp))],LO_NIBBLE(cpu_read8(status,temp)));
}
else{
syscall_handle(status, temp);
}
}
void instruction_bsr_lbl(cpu_status_t* status){
//int d = LO_NIBBLE(cpu_read8(status,status->pc)) + (HI_NIBBLE(cpu_read8(status,status->pc+1)) << 8) + (LO_NIBBLE(cpu_read8(status,status->pc+1)) << 16);
//int d = (int)(LO_NIBBLE(cpu_read8(status,status->pc)) << 16) + (int)(HI_NIBBLE(cpu_read8(status,status->pc+1)) << 8) + (int)(LO_NIBBLE(cpu_read8(status,status->pc+1)));
int d = (int)(LO_NIBBLE(cpu_read8(status,status->pc)) << 8) + (int)(HI_NIBBLE(cpu_read8(status,status->pc+1)) << 4) + (int)(LO_NIBBLE(cpu_read8(status,status->pc+1)));
int disp;
unsigned int temp;
temp = status->pc;
if ((d & 0x800) == 0)
disp = (0x00000FFF & d);
else
disp = (0xFFFFF000 | d);
status->pc += 2;
cpu_execute(status);
status->pc = temp;
status->pr = status->pc + 4;
status->pc = status->pc + 4 + (disp << 1);
printf("\e[34mpc: %8x jump (bsr) to %08x \e[39m\n", temp, status->pc);
}
void instruction_jsr_ar(cpu_status_t* status){
unsigned int temp;
temp = status->pc;
status->pc += 2;
cpu_execute(status);
status->pc = temp;
status->pr = status->pc + 4;
status->pc = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
printf("\e[34mpc: %8x jump (jsr) to %08x \e[39m\n", temp, status->pc);
}
void instruction_rts(cpu_status_t* status){
unsigned int temp;
temp = status->pc;
status->pc += 2;
cpu_execute(status);
status->pc = temp;
status->pc = status->pr;
printf("\e[34mpc: %8x jump (rts) to %08x \e[39m\n", temp, status->pr);
}
void instruction_bf_lbl(cpu_status_t* status){
int disp;
int temp = status->pc;
if ((cpu_read8(status,status->pc+1) & 0x80) == 0)
disp = (0x000000FF & cpu_read8(status,status->pc+1));
else
disp = (0xFFFFFF00 | cpu_read8(status,status->pc+1));
if (status->t == 0){
status->pc = status->pc + 4 + (disp << 1);
printf("\e[34mpc: %8x jump (bf) to %08x \e[39m\n", temp, status->pc);
}
else
status->pc += 2;
}
void instruction_bra_lbl(cpu_status_t* status){
int d = (int)(LO_NIBBLE(cpu_read8(status,status->pc)) << 8) + (int)(HI_NIBBLE(cpu_read8(status,status->pc+1)) << 4) + (int)(LO_NIBBLE(cpu_read8(status,status->pc+1)));
int disp;
unsigned int temp;
temp = status->pc;
if ((d & 0x800) == 0)
disp = (0x00000FFF & d);
else
disp = (0xFFFFF000 | d);
status->pc += 2;
cpu_execute(status);
status->pc = temp;
status->pc = status->pc + 4 + (disp << 1);
printf("\e[34mpc: %8x jump (bra) to %08x \e[39m\n", temp, status->pc);
}
void instruction_bt_lbl(cpu_status_t* status){
int disp;
int temp = status->pc;
if ((cpu_read8(status,status->pc+1) & 0x80) == 0)
disp = (0x000000FF & cpu_read8(status,status->pc+1));
else
disp = (0xFFFFFF00 | cpu_read8(status,status->pc+1));
if (status->t == 1){
status->pc = status->pc + 4 + (disp << 1);
printf("\e[34mpc: %8x jump (bt) to %08x \e[39m\n", temp, status->pc);
}
else
status->pc += 2;
}

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src/instructions/mov.c Normal file
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#include <cpu.h>
#include <instructions/instructions.h>
void instruction_mov_r_r(cpu_status_t* status) {
status->r[HI_NIBBLE(cpu_read8(status,status->pc))] = status->r[LO_NIBBLE(cpu_read8(status,status->pc+1))];
status->pc += 2;
}
void instruction_mov_imm_r(cpu_status_t* status){
if ((cpu_read8(status,status->pc+1) & 0x80) == 0)
status->r[HI_NIBBLE(cpu_read8(status,status->pc))] = (0x000000FF & cpu_read8(status,status->pc+1));
else
status->r[HI_NIBBLE(cpu_read8(status,status->pc))] = (0xFFFFFF00 | cpu_read8(status,status->pc+1));
status->pc += 2;
}

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src/instructions/movb.c Normal file
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#include <cpu.h>
#include <instructions/instructions.h>
void instruction_movb_ar_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read8(status,status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80) == 0)
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x000000FF;
else
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFFFF00;
status->pc += 2;
}
void instruction_movb_r_ar(cpu_status_t* status){
cpu_write8(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))], status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->pc += 2;
}
void instruction_movb_arp_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read8(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80) == 0)
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x000000FF;
else
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFFFF00;
if (LO_NIBBLE(cpu_read8(status,status->pc)) != HI_NIBBLE(cpu_read8(status,status->pc+1)))
status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] += 1;
status->pc += 2;
}
void instruction_movb_r_amr(cpu_status_t* status){
cpu_write8(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))] - 1, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= 1;
status->pc += 2;
}
void instruction_movb_disp_r_r0(cpu_status_t* status){
long disp = (0x0000000F & (long)LO_NIBBLE(cpu_read8(status,status->pc+1)));
status->r[0] = cpu_read8(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + disp);
if ((status->r[0] & 0x80) == 0)
status->r[0] &= 0x000000FF;
else
status->r[0] |= 0xFFFFFF00;
status->pc += 2;
}
void instruction_movb_r0_r_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read8(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + status->r[0]);
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80) == 0)
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x000000FF;
else status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFFFF00;
status->pc += 2;
}
void instruction_movb_r_r0_r(cpu_status_t* status){
cpu_write8(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))] + status->r[0], status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->pc += 2;
}
void instruction_movb_disp_gbr_r0(cpu_status_t* status){
unsigned int disp = (0x000000FF & cpu_read8(status,status->pc+1));
status->r[0] = cpu_read8(status, status->gbr + disp);
if ((status->r[0] & 0x80) == 0)
status->r[0] &= 0x000000FF;
else
status->r[0] |= 0xFFFFFF00;
status->pc += 2;
}

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src/instructions/movl.c Normal file
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#include <cpu.h>
#include <stdio.h>
#include <instructions/instructions.h>
/* mov.l @(disp,PC),Rn */
void instruction_movl_disp_pc_r(cpu_status_t* status) {
uint32_t disp = (0x000000FF & cpu_read8(status,status->pc+1));
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read32(status,(status->pc & 0xFFFFFFFC) + 4 + (disp << 2));
status->pc += 2;
}
void instruction_movl_ar_r(cpu_status_t* status) {
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read32(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->pc += 2;
}
void instruction_movl_r_ar(cpu_status_t* status) {
cpu_write32(status, LO_NIBBLE(cpu_read8(status,status->pc)), HI_NIBBLE(cpu_read8(status,status->pc+1)));
status->pc += 2;
}
void instruction_movl_arp_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read32(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
if (status->r[LO_NIBBLE(cpu_read8(status,status->pc))] != status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))])
status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] += 4;
status->pc += 2;
}
void instruction_movl_r_amr(cpu_status_t* status){
cpu_write32(status, LO_NIBBLE(cpu_read8(status,status->pc))-4, HI_NIBBLE(cpu_read8(status,status->pc+1)));
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= 4;
status->pc += 2;
}
void instruction_movl_disp_r_r(cpu_status_t* status){
long disp = (0x0000000F & (long)LO_NIBBLE(cpu_read8(status,status->pc+1)));
status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] = cpu_read32(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + (disp << 2));
status->pc += 2;
}
void instruction_movl_r_disp_r(cpu_status_t* status){
long disp = (0x0000000F & (long)LO_NIBBLE(cpu_read8(status,status->pc+1)));
cpu_write32(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + (disp << 2), status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->pc += 2;
}
void instruction_movl_r0_r_r(cpu_status_t* status){
status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] = cpu_read32(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + status->r[0]);
status->pc += 2;
}
void instruction_movl_r_r0_r(cpu_status_t* status){
cpu_write32(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))] + status->r[0], status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
status->pc += 2;
}
void instruction_movl_disp_gbr_r0(cpu_status_t* status){
unsigned int disp = (0x000000FF & cpu_read8(status,status->pc+1));
status->r[0] = cpu_read32(status, status->gbr + (disp << 2));
status->pc += 2;
}

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src/instructions/movw.c Normal file
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#include <cpu.h>
#include <instructions/instructions.h>
void instruction_movw_r0_disp_r(cpu_status_t* status){
long disp = (0x0000000F & (long)status->r[LO_NIBBLE(cpu_read8(status,status->pc+1))]);
cpu_write16(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + (disp << 1), status->r[0]);
status->pc += 2;
}

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src/instructions/operations.c Normal file
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#include <instructions/instructions.h>
void instruction_div1_r_r(cpu_status_t* status){
unsigned long tmp0, tmp2;
unsigned char old_q, tmp1;
old_q = status->q;
status->q = (0x80000000 & status->r[LO_NIBBLE(cpu_read8(status,status->pc))]) != 0;
tmp2 = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 1;
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= (unsigned long)status->t;
if (old_q == 0){
if (status->m == 0){
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= tmp2;
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] > tmp0;
if (status->q == 0)
status->q = tmp1;
else if (status->q == 1)
status->q = tmp1 == 0;
}
else if (status->m == 1)
{
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += tmp2;
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] < tmp0;
status->q = tmp1 == 0;
}
status->pc += 2;
}
}
void instruction_add_r_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
status->pc += 2;
}
void instruction_add_imm_r(cpu_status_t* status){
if ((cpu_read8(status,status->pc+1) & 0x80) == 0)
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += (0x000000FF & (long)cpu_read8(status,status->pc+1));
else
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += (0xFFFFFF00 | (long)cpu_read8(status,status->pc+1));
status->pc += 2;
}
void instruction_cmp_pz_r(cpu_status_t* status){
if ((long)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >= 0)
status->t = 1;
else
status->t = 0;
status->pc += 2;
}
void instruction_cmp_gt_r_r(cpu_status_t* status){
if ((long)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] > (long)status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))])
status->t = 1;
else
status->t = 0;
status->pc += 2;
}
void instruction_cmp_hs_r_r(cpu_status_t* status){
if ((unsigned long)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >= (unsigned long)status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))])
status->t = 1;
else
status->t = 0;
status->pc += 2;
}
void instruction_sub_r_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
status->pc += 2;
}

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src/instructions/shift.c Normal file
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#include <instructions/instructions.h>
void instruction_roctl_r(cpu_status_t* status){
long temp;
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80000000) == 0)
temp = 0;
else
temp = 1;
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 1;
if (status->t == 1)
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0x00000001;
else
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0xFFFFFFFE;
if (temp == 1)
status->t = 1;
else
status->t = 0;
status->pc += 2;
}

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src/instructions/system.c Normal file
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#include <instructions/instructions.h>
void instruction_nop(cpu_status_t* status){
status->pc += 2;
}
void instruction_stsl_mash_amr(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= 4;
cpu_write32(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))], status->mach);
status->pc += 2;
}
void instruction_stsl_macl_amr(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= 4;
cpu_write32(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))], status->macl);
status->pc += 2;
}
void instruction_stsl_pr_amr(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= 4;
cpu_write32(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))],status->pr);
status->pc += 2;
}
void instruction_clrt(cpu_status_t* status){
status->t = 0;
status->pc += 2;
}
void instruction_ldsl_arp_pr(cpu_status_t* status){
status->pr = cpu_read32(status, status->r[LO_NIBBLE(cpu_read8(status,status->pc))]);
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += 4;
status->pc += 2;
}

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src/log.c Normal file
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#include <log.h>
#include <stdio.h>
void log_mem_read_error(cpu_status_t* status, uint32_t addr){
printf("\e[31mpc: %8x memory read error at %08x \e[39m\n",status->pc, addr);
}
void log_mem_write_error(cpu_status_t* status, uint32_t addr){
printf("\e[31mpc: %8x memory write error at %08x \e[39m\n",status->pc, addr);
}

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src/log.h Normal file
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#include <cpu.h>
#pragma once
void log_mem_read_error(cpu_status_t* status, uint32_t addr);
void log_mem_write_error(cpu_status_t* status, uint32_t addr);

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src/main.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <cpu.h>
int main(int argc, char **argv){
if(argc < 2){
return 1;
}
if(!access(argv[1], F_OK ) == 0){
return 1;
}
cpu_status_t* status;
status = malloc(sizeof(cpu_status_t));
cpu_setup_addin(status, argv[1]);
printf("(ram read test) 0x08100000: %8x\n",cpu_read32(status,0x08100000));
printf("(rom read test) 0x00300200: %8x\n",cpu_read32(status,0x00300200));
cpu_run_from(status, 0x00300200);
return 0;
}

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src/syscall.c Normal file
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#include <syscall.h>
#include <stdio.h>
int syscall_handle(cpu_status_t* status, uint32_t origin){
printf("\e[32mpc: %8x syscall %8x\e[39m\n", origin, status->r[0]);
status->pc = status->pr;
}

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src/syscall.h Normal file
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#include <cpu.h>
#include <instructions/instructions.h>
#pragma once
int syscall_handle(cpu_status_t* status, uint32_t origin);