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émulation sh4 fonctionnel

This commit is contained in:
IniKiwi 2022-07-06 13:16:34 +02:00
parent 6055a42c67
commit 868fef0d4f
9 changed files with 71 additions and 12 deletions
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2
.gitignore vendored
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@ -4,5 +4,5 @@
/build/CMakeCache.txt
/build/nemu
/.vscode
/*.txt
aise.txt
Makefile

19
src/cpu.c
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@ -69,13 +69,13 @@ uint16_t cpu_read16(cpu_status_t* status, uint32_t addr){
if(addr >=0x08100000 && addr <= 0x08100000+32768){
uint16_t ret;
//ret = (uint16_t)status->ram[addr-0x08100000];
memcpy(&ret,&status->ram[addr-0x08100000],2);
ret = status->ram[addr-0x08100000+1];
ret <<= 8;
ret |= status->ram[addr-0x08100000];
return ret;
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
uint16_t ret;
ret = status->rom[addr-0x00300200+1];
ret <<= 8;
ret |= status->rom[addr-0x00300200];
@ -116,7 +116,6 @@ void cpu_write32(cpu_status_t* status, uint32_t addr, uint32_t data){
status->ram[addr-0x08100000+1] = (data >> 16) & 0xFF;
status->ram[addr-0x08100000+2] = (data >> 8) & 0xFF;
status->ram[addr-0x08100000+3] = data & 0xFF;
//memcpy(&status->ram[addr-0x08100000],&data, 4);
}
else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
memcpy(&status->rom[addr-0x00300200], &addr, 4);
@ -158,10 +157,10 @@ int cpu_execute(cpu_status_t* status){
LO_NIBBLE(cpu_read8(status,status->pc+1))
};
printf("pc: %8x r0: %8x r1: %8x r2: %8x r3: %8x r4: %8x r5: %8x r6: %8x\n",
status->pc,
printf("pc: %8x pr: %8x r0: %8x r1: %8x r2: %8x r3: %8x r4: %8x r5: %8x r6: %8x r15: %08x\n",
status->pc,status->pr,
status->r[0],status->r[1],status->r[2],status->r[3],
status->r[4],status->r[5],status->r[6]
status->r[4],status->r[5],status->r[6],status->r[15]
);
if(nibble[0] == 0b0110 && nibble[3] == 0b0011) instruction_mov_r_r(status);
@ -178,6 +177,7 @@ int cpu_execute(cpu_status_t* status){
else if(nibble[0] == 0b1100 && nibble[1] == 0b0110) instruction_movl_disp_gbr_r0(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b0001) instruction_movw_r0_disp_r(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b0101) instruction_movw_disp_r_r0(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b0000) instruction_movb_ar_r(status);
else if(nibble[0] == 0b0010 && nibble[3] == 0b0000) instruction_movb_r_ar(status);
@ -196,7 +196,9 @@ int cpu_execute(cpu_status_t* status){
else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0001) instruction_cmp_pz_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b0111) instruction_cmp_gt_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b0010) instruction_cmp_hs_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b1000) instruction_add_r_r(status);
else if(nibble[0] == 0b0011 && nibble[3] == 0b1000) instruction_sub_r_r(status);
else if(nibble[0] == 0b0110 && nibble[3] == 0b1101) instruction_extuw_r_r(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0101) instruction_cmp_pl_r(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b1011) instruction_jmp_r(status);
else if(nibble[0] == 0b1011) instruction_bsr_lbl(status);
@ -205,6 +207,7 @@ int cpu_execute(cpu_status_t* status){
else if(nibble[0] == 0b1000 && nibble[1] == 0b1011 ) instruction_bf_lbl(status);
else if(nibble[0] == 0b1010) instruction_bra_lbl(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b1001 ) instruction_bt_lbl(status);
else if(nibble[0] == 0b1000 && nibble[1] == 0b1101 ) instruction_bts_lbl(status);
else if(nibble[0] == 0b0000 && nibble[1] == 0b0000 && nibble[2] == 0b0000 && nibble[3] == 0b1001) instruction_nop(status);
else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b0010) instruction_stsl_mash_amr(status);

1
src/cpu.h
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@ -13,6 +13,7 @@ typedef struct{
uint8_t* rom;
uint8_t ram[32768]; // 0x08100000
uint8_t vram[1024];
uint32_t program_size;

4
src/instructions/instructions.h
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@ -18,6 +18,7 @@ void instruction_movl_r_r0_r(cpu_status_t*);
void instruction_movl_disp_gbr_r0(cpu_status_t*);
void instruction_movw_r0_disp_r(cpu_status_t* status);
void instruction_movw_disp_r_r0(cpu_status_t* status);
void instruction_movb_ar_r(cpu_status_t* status);
void instruction_movb_r_ar(cpu_status_t* status);
@ -37,6 +38,8 @@ void instruction_cmp_pz_r(cpu_status_t* status);
void instruction_cmp_gt_r_r(cpu_status_t* status);
void instruction_cmp_hs_r_r(cpu_status_t* status);
void instruction_sub_r_r(cpu_status_t* status);
void instruction_extuw_r_r(cpu_status_t* status);
void instruction_cmp_pl_r(cpu_status_t* status);
void instruction_jmp_r(cpu_status_t* status);
void instruction_bsr_lbl(cpu_status_t* status);
@ -45,6 +48,7 @@ void instruction_rts(cpu_status_t* status);
void instruction_bf_lbl(cpu_status_t* status);
void instruction_bra_lbl(cpu_status_t* status);
void instruction_bt_lbl(cpu_status_t* status);
void instruction_bts_lbl(cpu_status_t* status);
void instruction_nop(cpu_status_t* status);
void instruction_stsl_mash_amr(cpu_status_t* status);

20
src/instructions/jmp.c
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@ -117,4 +117,24 @@ void instruction_bt_lbl(cpu_status_t* status){
}
else
status->pc += 2;
}
void instruction_bts_lbl(cpu_status_t* status){
int disp;
unsigned temp;
temp = status->pc;
status->pc += 2;
cpu_execute(status);
status->pc = temp;
if ((cpu_read8(status,status->pc+1) & 0x80) == 0)
disp = (0x000000FF & cpu_read8(status,status->pc+1));
else
disp = (0xFFFFFF00 | cpu_read8(status,status->pc+1));
if (status->t == 1)
status->pc = status->pc + 4 + (disp << 1);
else
status->pc += 4;
}

11
src/instructions/movw.c
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@ -7,3 +7,14 @@ void instruction_movw_r0_disp_r(cpu_status_t* status){
status->pc += 2;
}
void instruction_movw_disp_r_r0(cpu_status_t* status){
long disp = (0x0000000F & (long)status->r[LO_NIBBLE(cpu_read8(status,status->pc+1))]);
status->r[0] = cpu_read16(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + (disp << 1));
if ((status->r[0] & 0x8000) == 0)
status->r[0] &= 0x0000FFFF;
else
status->r[0] |= 0xFFFF0000;
status->pc += 2;
}

15
src/instructions/operations.c
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@ -78,4 +78,19 @@ void instruction_cmp_hs_r_r(cpu_status_t* status){
void instruction_sub_r_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
status->pc += 2;
}
void instruction_extuw_r_r(cpu_status_t* status){
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x0000FFFF;
status->pc += 2;
}
void instruction_cmp_pl_r(cpu_status_t* status){
if ((long)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] > 0)
status->t = 1;
else
status->t = 0;
status->pc += 2;
}

7
src/main.c
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@ -13,11 +13,12 @@ int main(int argc, char **argv){
}
cpu_status_t* status;
status = malloc(sizeof(cpu_status_t));
status = malloc(sizeof(cpu_status_t));
cpu_setup_addin(status, argv[1]);
status->r[15] = 0x08100200;
printf("(ram read test) 0x08100000: %8x\n",cpu_read32(status,0x08100000));
cpu_write32(status,0x08100004, 0x00560000);
printf("(ram write test) 0x00560000 at 0x08100004. result: %8x\n", cpu_read32(status,0x08100004));
printf("(rom read test) 0x00300200: %8x\n",cpu_read32(status,0x00300200));
cpu_run_from(status, 0x00300200);

4
src/syscall/mmu.c Normal file
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@ -0,0 +1,4 @@
#include <syscall.h>
void syscall_hmem_set_mmu(){
}