correction de div1
ajout d'opcodes le menu de orton and the princess s'affiche correction d'affichage getkey fonctionel seulement pour exe,shift et haut
This commit is contained in:
IniKiwi
parent
0865fb9d39
commit
ef6bbf62e2
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@ -20,6 +20,7 @@ set(SRCS
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src/instructions/system.c
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src/log.c
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src/memory.c
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src/syscall/keyboard.c
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)
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find_package(SDL2 REQUIRED)
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File diff suppressed because it is too large
Load Diff
65
src/cpu.c
65
src/cpu.c
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@ -79,16 +79,16 @@ uint16_t cpu_read16(cpu_status_t* status, uint32_t addr){
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if(addr >=0x08100000 && addr <= 0x08100000+524288){
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uint16_t ret;
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//ret = (uint16_t)status->ram[addr-0x08100000];
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ret = status->ram[addr-0x08100000+1];
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ret = status->ram[addr-0x08100000];
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ret <<= 8;
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ret |= status->ram[addr-0x08100000];
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ret |= status->ram[addr-0x08100000+1];
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return ret;
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}
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else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
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uint16_t ret;
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ret = status->rom[addr-0x00300200+1];
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ret = status->rom[addr-0x00300200];
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ret <<= 8;
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ret |= status->rom[addr-0x00300200];
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ret |= status->rom[addr-0x00300200+1];
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//memcpy(&ret,&status->ram[addr-0x00300000],1);
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//ret = (uint16_t)status->rom[addr-0x00300000];
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@ -140,6 +140,7 @@ void cpu_write32(cpu_status_t* status, uint32_t addr, uint32_t data){
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status->vram[addr-0x01100000+1] = (data >> 16) & 0xFF;
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status->vram[addr-0x01100000+2] = (data >> 8) & 0xFF;
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status->vram[addr-0x01100000+3] = data & 0xFF;
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display_update(status->display, status);
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}
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else{
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log_mem_write_error(status, addr);
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@ -153,6 +154,9 @@ void cpu_write16(cpu_status_t* status, uint32_t addr, uint16_t data){
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/*else if(addr >=0x00300200 && addr <= 0x00300200+status->program_size){
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memcpy(&status->rom[addr-0x00300200], &addr, 2);
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}*/
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else if(addr == 0xa4000102 || addr == 0xa4000118){
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}
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else{
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log_mem_write_error(status, addr);
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}
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@ -167,6 +171,9 @@ void cpu_write8(cpu_status_t* status, uint32_t addr, uint8_t data){
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}*/
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else if(addr >=0x01100000 && addr <= 0x01100000+8192){
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status->vram[addr-0x01100000] = data;
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}
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else if(addr == 0xb4000000 || addr == 0xb4010000){
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}
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else{
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log_mem_write_error(status, addr);
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@ -196,6 +203,9 @@ int cpu_execute(cpu_status_t* status){
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if(nibble[0] == 0b0110 && nibble[3] == 0b0011) instruction_mov_r_r(status);
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else if(nibble[0] == 0b1110) instruction_mov_imm_r(status);
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else if(nibble[0] == 0b0000 && nibble[2] == 0b0010 && nibble[3] == 0b1001) instruction_movt_r(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b1000) instruction_swapb_r_r(status);
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else if(nibble[0] == 0b1101) instruction_movl_disp_pc_r(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b0010) instruction_movl_ar_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b0010) instruction_movl_r_ar(status);
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@ -212,6 +222,10 @@ int cpu_execute(cpu_status_t* status){
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else if(nibble[0] == 0b1001) instruction_movw_disp_pc_r0(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b0001) instruction_movw_r_ar(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b0101) instruction_movw_arp_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b0001) instruction_movw_r0_disp_gbr(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b0001) instruction_movw_ar_r(status);
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else if(nibble[0] == 0b0000 && nibble[3] == 0b1101) instruction_movw_r0_r_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b0101) instruction_movw_disp_gbr_r0(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b0000) instruction_movb_ar_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b0000) instruction_movb_r_ar(status);
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@ -222,12 +236,21 @@ int cpu_execute(cpu_status_t* status){
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else if(nibble[0] == 0b0000 && nibble[3] == 0b0100) instruction_movb_r_r0_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b0100) instruction_movb_disp_gbr_r0(status);
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else if(nibble[0] == 0b1000 && nibble[1] == 0b0000) instruction_movb_r0_disp_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b0000) instruction_movb_r0_disp_gbr(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0100) instruction_roctl_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0001) instruction_shar_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b1000) instruction_shll2_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b0001) instruction_shlr_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b1001) instruction_shlr2_r(status);
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else if(nibble[0] == 0b0100 && nibble[3] == 0b1101) instruction_shld_r_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0000 && nibble[3] == 0b0000) instruction_shll_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b1000) instruction_shll16_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b1000) instruction_shll8_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0101) instruction_rotcr_r(status);
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else if(nibble[0] == 0b0100 && nibble[3] == 0b1100) instruction_shad_r_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b1001) instruction_shlr16_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b1001) instruction_shlr8_r(status);
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else if(nibble[0] == 0b0011 && nibble[3] == 0b0100) instruction_div1_r_r(status);
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else if(nibble[0] == 0b0011 && nibble[3] == 0b1100) instruction_add_r_r(status);
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@ -243,6 +266,14 @@ int cpu_execute(cpu_status_t* status){
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else if(nibble[0] == 0b0011 && nibble[3] == 0b0011) instruction_cmp_ge_r_r(status);
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else if(nibble[0] == 0b0000 && nibble[3] == 0b0111) instruction_mull_r_r(status);
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else if(nibble[0] == 0b0011 && nibble[3] == 0b0000) instruction_cmp_eq_r_r(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b1100) instruction_extub_r_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0000) instruction_dt_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b0111) instruction_div0s_r_r(status);
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else if(nibble[0] == 0b0011 && nibble[3] == 0b1110) instruction_addc_r_r(status);
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else if(nibble[0] == 0b0011 && nibble[3] == 0b1010) instruction_subc_r_r(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b1110) instruction_extsb_r_r(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b1011) instruction_neg_r_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b1100) instruction_cmp_str_r_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b1011) instruction_jmp_r(status);
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else if(nibble[0] == 0b1011) instruction_bsr_lbl(status);
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@ -263,11 +294,18 @@ int cpu_execute(cpu_status_t* status){
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0010 && nibble[3] == 0b0110) instruction_ldsl_arp_pr(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b0110) instruction_ldsl_arp_macl(status);
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else if(nibble[0] == 0b0000 && nibble[2] == 0b0001 && nibble[3] == 0b1010) instruction_sts_macl_r(status);
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else if(nibble[0] == 0b0100 && nibble[2] == 0b0001 && nibble[3] == 0b1110) instruction_ldc_r_gbr(status);
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else if(nibble[0] == 0b0000 && nibble[2] == 0b0001 && nibble[3] == 0b0010) instruction_stc_gbr_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b1000) instruction_tst_r_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b1011) instruction_or_r_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b1001) instruction_and_r_r(status);
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else if(nibble[0] == 0b0010 && nibble[3] == 0b1010) instruction_xor_r_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b1001) instruction_and_imm_r0(status);
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else if(nibble[0] == 0b0110 && nibble[3] == 0b0111) instruction_not_r_r(status);
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else if(nibble[0] == 0b1100 && nibble[1] == 0b1011) instruction_or_imm_r0(status);
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else{ printf("\e[33mpc: %8x unkdown opcode, skipping...\e[39m\n",status->pc);status->pc += 2;return 1;}
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else{ printf("\e[33mpc: %8x unkdown opcode, skipping...\e[39m\n",status->pc);status->pc += 2;exit(1);return 1;}
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return 0;
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}
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@ -276,15 +314,22 @@ int cpu_run_from(cpu_status_t* status, uint32_t addr){
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int total_error = 0;
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int total_executions = 0;
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while (status->pc-0x00300200 < status->program_size){
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//while (status->pc-0x00300200 < status->program_size){
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while (status->pc-0x00300200 < status->program_size || ( status->pc >= 0x08100000 && status->pc <= 0x08100000+524288 )){
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// TODO: better kerboard gestion
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SDL_PumpEvents();
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const unsigned char* key = SDL_GetKeyboardState(NULL);
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if (key[SDL_SCANCODE_ESCAPE]) {
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exit(0);
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}
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if(cpu_execute(status)){
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printf("err\n");
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total_error++;
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}
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total_executions++;
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if(total_executions > 100000000){
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//total_executions++;
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/*if(total_executions > 100000){
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break;
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}
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}*/
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}
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printf("excution terminated with %d not found opcodes\n",total_error);
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@ -27,23 +27,21 @@ void display_clear(display_t* display){
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}
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#define HIGH_BIT(b) ((b & 0x80) >> 7)
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#define LO_BIT(b) ((b >> 0) & 1)
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void display_update(display_t* display, cpu_status_t* status){
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uint8_t screen[8*1024];
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for(int i=0; i<1024;i++){
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display_clear(display);
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for(int i=0; i<1024; i++){
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uint8_t byte = status->vram[i];
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for(int b=0; b<8;b++){
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screen[i*8+b] = HIGH_BIT(byte >> b);
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}
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}
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for(int i=0; i<64;i++){
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for(int b=0; b<128;b++){
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if(screen[i*128+b] == 1){
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display_pixel_on(display, b, i);
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} else {
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display_pixel_off(display, b, i);
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if(HIGH_BIT(byte << b) == 1){
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int nb = b+1;
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int y = i/16;
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int x = (i%16)*8+b;
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display_pixel_on(display, x , y);
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}
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}
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}
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}
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SDL_RenderPresent(display->renderer);
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}
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@ -5,6 +5,8 @@
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void instruction_mov_r_r(cpu_status_t*);
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void instruction_mov_imm_r(cpu_status_t*);
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void instruction_movt_r(cpu_status_t* status);
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void instruction_swapb_r_r(cpu_status_t* status);
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void instruction_movl_disp_pc_r(cpu_status_t*);
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void instruction_movl_ar_r(cpu_status_t*);
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@ -22,6 +24,10 @@ void instruction_movw_disp_r_r0(cpu_status_t* status);
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void instruction_movw_disp_pc_r0 (cpu_status_t* status);
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void instruction_movw_r_ar(cpu_status_t* status);
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void instruction_movw_arp_r(cpu_status_t* status);
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void instruction_movw_r0_disp_gbr(cpu_status_t* status);
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void instruction_movw_ar_r(cpu_status_t* status);
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void instruction_movw_r0_r_r(cpu_status_t* status);
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void instruction_movw_disp_gbr_r0(cpu_status_t* status);
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void instruction_movb_ar_r(cpu_status_t* status);
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void instruction_movb_r_ar(cpu_status_t* status);
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@ -32,12 +38,21 @@ void instruction_movb_r0_r_r(cpu_status_t* status);
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void instruction_movb_r_r0_r (cpu_status_t* status);
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void instruction_movb_disp_gbr_r0(cpu_status_t* status);
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void instruction_movb_r0_disp_r(cpu_status_t* status);
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void instruction_movb_r0_disp_gbr(cpu_status_t* status);
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void instruction_roctl_r(cpu_status_t* status);
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void instruction_shar_r(cpu_status_t* status);
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void instruction_shll2_r(cpu_status_t* status);
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void instruction_shlr_r(cpu_status_t* status);
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void instruction_shlr2_r(cpu_status_t* status);
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void instruction_shld_r_r(cpu_status_t* status);
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void instruction_shll_r(cpu_status_t* status);
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void instruction_shll16_r(cpu_status_t* status);
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void instruction_shll8_r(cpu_status_t* status);
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void instruction_rotcr_r (cpu_status_t* status);
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void instruction_shad_r_r(cpu_status_t* status);
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void instruction_shlr16_r(cpu_status_t* status);
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void instruction_shlr8_r(cpu_status_t* status);
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void instruction_div1_r_r(cpu_status_t* status);
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void instruction_add_r_r(cpu_status_t* status);
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@ -53,6 +68,14 @@ void instruction_cmp_hi_r_r(cpu_status_t* status);
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void instruction_cmp_ge_r_r(cpu_status_t* status);
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void instruction_mull_r_r(cpu_status_t* status);
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void instruction_cmp_eq_r_r(cpu_status_t* status);
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void instruction_extub_r_r(cpu_status_t* status);
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void instruction_dt_r(cpu_status_t* status);
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void instruction_div0s_r_r(cpu_status_t* status);
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void instruction_addc_r_r(cpu_status_t* status);
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void instruction_subc_r_r(cpu_status_t* status);
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void instruction_extsb_r_r(cpu_status_t* status);
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void instruction_neg_r_r(cpu_status_t* status);
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void instruction_cmp_str_r_r(cpu_status_t* status);
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void instruction_jmp_r(cpu_status_t* status);
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void instruction_bsr_lbl(cpu_status_t* status);
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@ -72,6 +95,13 @@ void instruction_clrt(cpu_status_t* status);
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void instruction_ldsl_arp_pr(cpu_status_t* status);
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void instruction_ldsl_arp_macl(cpu_status_t* status);
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void instruction_sts_macl_r(cpu_status_t* status);
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void instruction_ldc_r_gbr(cpu_status_t* status);
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void instruction_stc_gbr_r(cpu_status_t* status);
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void instruction_tst_r_r(cpu_status_t* status);
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void instruction_or_r_r(cpu_status_t* status);
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void instruction_or_r_r(cpu_status_t* status);
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void instruction_and_r_r(cpu_status_t* status);
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void instruction_xor_r_r(cpu_status_t* status);
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void instruction_and_imm_r0(cpu_status_t* status);
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void instruction_not_r_r(cpu_status_t* status);
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void instruction_or_imm_r0(cpu_status_t* status);
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@ -5,11 +5,12 @@
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void instruction_jmp_r(cpu_status_t* status){
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unsigned int temp;
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temp = status->pc;
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uint32_t a = status->r[LO_NIBBLE(cpu_read8(status,temp))];
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status->pc += 2;
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cpu_execute(status);
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status->pc = temp;
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if(status->r[LO_NIBBLE(cpu_read8(status,temp))] != 0x80010070){
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status->pc = status->r[LO_NIBBLE(cpu_read8(status,temp))];
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status->pc = a;
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printf("\e[34mpc: %8x jump to %08x (r%02d)\e[39m\n", temp, status->r[LO_NIBBLE(cpu_read8(status,temp))],LO_NIBBLE(cpu_read8(status,temp)));
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}
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else{
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@ -44,15 +45,20 @@ void instruction_bsr_lbl(cpu_status_t* status){
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void instruction_jsr_ar(cpu_status_t* status){
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unsigned int temp;
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temp = status->pc;
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uint32_t a = status->r[LO_NIBBLE(cpu_read8(status,temp))];
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status->pc += 2;
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cpu_execute(status);
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status->pc = temp;
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status->pr = status->pc + 4;
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status->pc = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
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|
||||
printf("\e[34mpc: %8x jump (jsr) to %08x \e[39m\n", temp, status->pc);
|
||||
if(a == 0x80010070){
|
||||
syscall_handle(status, temp);
|
||||
}
|
||||
else{
|
||||
status->pr = temp + 4;
|
||||
status->pc = a;
|
||||
printf("\e[34mpc: %8x jump (jsr) to %08x \e[39m\n", temp, status->pc);
|
||||
}
|
||||
}
|
||||
|
||||
void instruction_rts(cpu_status_t* status){
|
||||
|
|
|
|||
|
|
@ -12,4 +12,29 @@ void instruction_tst_r_r(cpu_status_t* status){
|
|||
void instruction_or_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_and_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_xor_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] ^= status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_and_imm_r0(cpu_status_t* status){
|
||||
status->r[0] &= (0x000000FF & (long)cpu_read8(status,status->pc+1));
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_not_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = ~status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_or_imm_r0(cpu_status_t* status){
|
||||
status->r[0] |= (0x000000FF & (long)cpu_read8(status,status->pc+1));
|
||||
status->pc += 2;
|
||||
}
|
||||
|
|
@ -13,4 +13,23 @@ void instruction_mov_imm_r(cpu_status_t* status){
|
|||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = (0xFFFFFF00 | cpu_read8(status,status->pc+1));
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_movt_r(cpu_status_t* status){
|
||||
if (status->t == 1)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0x00000001;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0x00000000;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_swapb_r_r(cpu_status_t* status){
|
||||
int n = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
int m = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
unsigned long temp0, temp1;
|
||||
temp0 = status->r[m] & 0xFFFF0000;
|
||||
temp1 = (status->r[m] & 0x000000FF) << 8;
|
||||
status->r[n] = (status->r[m] & 0x0000FF00) >> 8;
|
||||
status->r[n] = status->r[n] | temp1 | temp0;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
|
@ -79,4 +79,12 @@ void instruction_movb_r0_disp_r(cpu_status_t* status){
|
|||
long disp = (0x0000000F & (long)d);
|
||||
cpu_write8(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + disp, status->r[0]);
|
||||
status->pc += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void instruction_movb_r0_disp_gbr(cpu_status_t* status){
|
||||
int d = LO_NIBBLE(cpu_read8(status,status->pc+1));
|
||||
unsigned int disp = (0x000000FF & d);
|
||||
cpu_write8(status, status->gbr + disp, status->r[0]);
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -48,4 +48,45 @@ void instruction_movw_arp_r(cpu_status_t* status){
|
|||
status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] += 2;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void instruction_movw_r0_disp_gbr(cpu_status_t* status){
|
||||
unsigned int disp = (0x000000FF & cpu_read8(status,status->pc+1));
|
||||
cpu_write16(status, status->gbr + (disp << 1), status->r[0]);
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_movw_ar_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read16(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))]);
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x8000) == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x0000FFFF;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFF0000;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_movw_r0_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = cpu_read16(status, status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] + status->r[0]);
|
||||
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x8000) == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x0000FFFF;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFF0000;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_movw_disp_gbr_r0(cpu_status_t* status){
|
||||
int d = cpu_read8(status,status->pc+1);
|
||||
unsigned int disp = (0x000000FF & d);
|
||||
status->r[0] = cpu_read16(status, status->gbr + (disp << 1));
|
||||
|
||||
if ((status->r[0] & 0x8000) == 0)
|
||||
status->r[0] &= 0x0000FFFF;
|
||||
else
|
||||
status->r[0] |= 0xFFFF0000;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,37 +3,72 @@
|
|||
void instruction_div1_r_r(cpu_status_t* status){
|
||||
unsigned long tmp0, tmp2;
|
||||
unsigned char old_q, tmp1;
|
||||
int n = LO_NIBBLE(cpu_read8(status,status->pc));
|
||||
int m = HI_NIBBLE(cpu_read8(status,status->pc+1));
|
||||
|
||||
old_q = status->q;
|
||||
status->q = (0x80000000 & status->r[LO_NIBBLE(cpu_read8(status,status->pc))]) != 0;
|
||||
tmp2 = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 1;
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= (unsigned long)status->t;
|
||||
status->q = (0x80000000 & status->r[n]) != 0;
|
||||
tmp2 = status->r[m];
|
||||
status->r[n] <<= 1;
|
||||
status->r[n] |= (unsigned long)status->t;
|
||||
|
||||
if (old_q == 0){
|
||||
if (status->m == 0){
|
||||
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] -= tmp2;
|
||||
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] > tmp0;
|
||||
if (old_q == 0)
|
||||
{
|
||||
if (status->m == 0)
|
||||
{
|
||||
tmp0 = status->r[n];
|
||||
status->r[n] -= tmp2;
|
||||
tmp1 = status->r[n] > tmp0;
|
||||
|
||||
if (status->q == 0)
|
||||
status->q = tmp1;
|
||||
else if (status->q == 1)
|
||||
status->q = tmp1 == 0;
|
||||
if (status->q == 0)
|
||||
status->q = tmp1;
|
||||
else if (status->q == 1)
|
||||
status->q = tmp1 == 0;
|
||||
}
|
||||
|
||||
else if (status->m == 1)
|
||||
{
|
||||
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += tmp2;
|
||||
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] < tmp0;
|
||||
tmp0 = status->r[n];
|
||||
status->r[n] += tmp2;
|
||||
tmp1 = status->r[n] < tmp0;
|
||||
|
||||
if (status->q == 0)
|
||||
status->q = tmp1 == 0;
|
||||
else if (status->q == 1)
|
||||
status->q = tmp1;
|
||||
}
|
||||
}
|
||||
|
||||
else if (old_q == 1)
|
||||
{
|
||||
if (status->m == 0)
|
||||
{
|
||||
tmp0 = status->r[n];
|
||||
status->r[n] += tmp2;
|
||||
tmp1 = status->r[n] < tmp0;
|
||||
|
||||
if (status->q == 0)
|
||||
status->q = tmp1;
|
||||
else if (status->q == 1)
|
||||
status->q = tmp1 == 0;
|
||||
}
|
||||
|
||||
else if (status->m == 1)
|
||||
{
|
||||
tmp0 = status->r[n];
|
||||
status->r[n] -= tmp2;
|
||||
tmp1 = status->r[n] > tmp0;
|
||||
|
||||
if (status->q == 0)
|
||||
status->q = tmp1 == 0;
|
||||
else if (status->q == 1)
|
||||
status->q = tmp1;
|
||||
}
|
||||
}
|
||||
|
||||
status->t = (status->q == status->m);
|
||||
status->pc += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void instruction_add_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] += status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
|
|
@ -141,5 +176,104 @@ void instruction_cmp_eq_r_r(cpu_status_t* status){
|
|||
else
|
||||
status->t = 0;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_extub_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x000000FF;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_dt_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))]--;
|
||||
|
||||
if (status->r[LO_NIBBLE(cpu_read8(status,status->pc))] == 0)
|
||||
status->t = 1;
|
||||
else status->t = 0;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_div0s_r_r(cpu_status_t* status){
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80000000) == 0)
|
||||
status->q = 0;
|
||||
else
|
||||
status->q = 1;
|
||||
|
||||
if ((status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x80000000) == 0)
|
||||
status->m = 0;
|
||||
else
|
||||
status->m = 1;
|
||||
|
||||
status->t = ! (status->m == status->q);
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_addc_r_r(cpu_status_t* status){
|
||||
unsigned long tmp0, tmp1;
|
||||
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] + status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = tmp1 + status->t;
|
||||
|
||||
if (tmp0>tmp1)
|
||||
status->t = 1;
|
||||
else
|
||||
status->t = 0;
|
||||
|
||||
if (tmp1 > status->r[LO_NIBBLE(cpu_read8(status,status->pc))])
|
||||
status->t = 1;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_subc_r_r(cpu_status_t* status){
|
||||
unsigned long tmp0, tmp1;
|
||||
tmp1 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] - status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
tmp0 = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = tmp1 - status->t;
|
||||
|
||||
if (tmp0 < tmp1)
|
||||
status->t = 1;
|
||||
else
|
||||
status->t = 0;
|
||||
|
||||
if (tmp1 < status->r[LO_NIBBLE(cpu_read8(status,status->pc))])
|
||||
status->t = 1;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_extsb_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
|
||||
if ((status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x00000080) == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x000000FF;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0xFFFFFF00;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_neg_r_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0 - status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_cmp_str_r_r(cpu_status_t* status){
|
||||
unsigned long temp;
|
||||
long HH, HL, LH, LL;
|
||||
temp = status->r[LO_NIBBLE(cpu_read8(status,status->pc))] ^ status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))];
|
||||
HH = (temp & 0xFF000000) >> 24;
|
||||
HL = (temp & 0x00FF0000) >> 16;
|
||||
LH = (temp & 0x0000FF00) >> 8;
|
||||
LL = temp & 0x000000FF;
|
||||
HH = HH && HL && LH && LL;
|
||||
|
||||
if (HH == 0)
|
||||
status->t = 1;
|
||||
else
|
||||
status->t = 0;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
|
@ -65,4 +65,90 @@ void instruction_shlr2_r(cpu_status_t* status){
|
|||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >>= 2;
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x3FFFFFFF;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shld_r_r(cpu_status_t* status){
|
||||
int sgn = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x80000000;
|
||||
|
||||
if (sgn == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= (status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F);
|
||||
else if ((status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F) == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = (unsigned)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >> ((~status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F) + 1);
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shll_r(cpu_status_t* status){
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80000000) == 0)
|
||||
status->t = 0;
|
||||
else
|
||||
status->t = 1;
|
||||
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 1;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shll16_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 16;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shll8_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= 8;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_rotcr_r (cpu_status_t* status){
|
||||
long temp;
|
||||
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x00000001) == 0)
|
||||
temp = 0;
|
||||
else
|
||||
temp = 1;
|
||||
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >>= 1;
|
||||
|
||||
if (status->t == 1)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] |= 0x80000000;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x7FFFFFFF;
|
||||
|
||||
if (temp == 1)
|
||||
status->t = 1;
|
||||
else
|
||||
status->t = 0;
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shad_r_r(cpu_status_t* status){
|
||||
int sgn = status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x80000000;
|
||||
|
||||
if (sgn == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] <<= (status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F);
|
||||
else if ((status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F) == 0)
|
||||
{
|
||||
if ((status->r[LO_NIBBLE(cpu_read8(status,status->pc))] & 0x80000000) == 0)
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0;
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = 0xFFFFFFFF;
|
||||
}
|
||||
else
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = (long)status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >> ((~status->r[HI_NIBBLE(cpu_read8(status,status->pc+1))] & 0x1F) + 1);
|
||||
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shlr16_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >>= 16;
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x0000FFFF;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_shlr8_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] >>= 8;
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] &= 0x00FFFFFF;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
|
@ -44,4 +44,14 @@ void instruction_ldsl_arp_macl(cpu_status_t* status){
|
|||
void instruction_sts_macl_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = status->macl;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_ldc_r_gbr(cpu_status_t* status){
|
||||
status->gbr = status->r[LO_NIBBLE(cpu_read8(status,status->pc))];
|
||||
status->pc += 2;
|
||||
}
|
||||
|
||||
void instruction_stc_gbr_r(cpu_status_t* status){
|
||||
status->r[LO_NIBBLE(cpu_read8(status,status->pc))] = status->gbr;
|
||||
status->pc += 2;
|
||||
}
|
||||
|
|
@ -10,5 +10,6 @@ int syscall_handle(cpu_status_t* status, uint32_t origin){
|
|||
if(id == 0x808) syscall_print(status);
|
||||
if(id == 0x135) syscall_get_vram_address(status);
|
||||
if(id == 0xacd) syscall_malloc(status);
|
||||
if(id == 0x90f) syscall_getkey(status);
|
||||
status->pc = status->pr;
|
||||
}
|
||||
|
|
@ -10,4 +10,6 @@ void syscall_get_vram_address(cpu_status_t* status);
|
|||
void syscall_locate(cpu_status_t* status);
|
||||
void syscall_print(cpu_status_t* status);
|
||||
|
||||
void syscall_malloc(cpu_status_t* status);
|
||||
void syscall_malloc(cpu_status_t* status);
|
||||
|
||||
void syscall_getkey(cpu_status_t* status);
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#include <syscall.h>
|
||||
|
||||
void syscall_getkey(cpu_status_t* status){
|
||||
while(true){
|
||||
SDL_PumpEvents();
|
||||
const unsigned char* key = SDL_GetKeyboardState(NULL);
|
||||
if (key[SDL_SCANCODE_RETURN]) { //exe
|
||||
cpu_write32(status, status->r[4],(int) 30004);
|
||||
return;
|
||||
}
|
||||
else if(key[SDL_SCANCODE_UP]) { //up
|
||||
cpu_write32(status, status->r[4],(int) 30018);
|
||||
return;
|
||||
}
|
||||
else if(key[SDL_SCANCODE_A]) { //shift
|
||||
cpu_write32(status, status->r[4],(int) 30006);
|
||||
return;
|
||||
}
|
||||
else if (key[SDL_SCANCODE_ESCAPE]) {
|
||||
exit(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue