PythonExtra/docs/samd
robert-hh 76cf98c35b samd/mcu: Implement a hardware seed for the SAMD21 random module.
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock.
Even if both use the same reference source, they have a different jitter.
SysTick is driven by FDPLL96M, the us counter by DFLL48M.  As a random
source, the us counter is read out on every SysTick and the value is used
to accumulate a simple multiply, add and xor register.  According to tests
it creates about 30 bit random bit-flips per second.  That mechanism will
pass quite a few RNG tests, has a suitable frequency distribution and
serves better than just the time after boot to seed the PRNG.
2023-02-21 23:15:29 +11:00
..
img docs/samd: Add documentation for the samd port. 2022-10-26 23:39:35 +11:00
tutorial docs/samd: Add documentation for the samd port. 2022-10-26 23:39:35 +11:00
general.rst docs/samd: Add documentation for the samd port. 2022-10-26 23:39:35 +11:00
pinout.rst docs/samd/pinout: Fix the pin numbering for the default assignments. 2022-11-08 23:24:35 +11:00
quickref.rst samd/mcu: Implement a hardware seed for the SAMD21 random module. 2023-02-21 23:15:29 +11:00