2019-12-28 17:18:13 +01:00
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//---
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2020-02-12 07:53:00 +01:00
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// fxos.passes.pcrel: Resolution of PC-relative addresses
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2019-12-28 17:18:13 +01:00
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//---
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2020-02-12 07:53:00 +01:00
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#include <fxos/disasm-passes/pcrel.h>
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2019-12-28 17:18:13 +01:00
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namespace FxOS {
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PcrelPass::PcrelPass(Disassembly &disasm):
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DisassemblyPass(disasm)
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{
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}
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void PcrelPass::analyze(uint32_t pc, ConcreteInstruction &ci)
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{
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2020-02-12 07:53:00 +01:00
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Instruction const &i = ci.inst;
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for(size_t n = 0; n < i.args.size(); n++)
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{
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Argument const &a = i.args[n];
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ConcreteInstructionArg &ca = ci.args[n];
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if(a.kind == Argument::PcRel)
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{
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2020-02-12 16:33:08 +01:00
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uint32_t addr = (pc & ~(a.opsize - 1)) + 4 + a.disp;
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ca.location = RelConstDomain().constant(addr);
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/* Also compute the value. This is sign-extended from
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16-bit with mov.w. There is no mov.b for this
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instruction. */
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Target &t = m_disasm.target();
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uint32_t v;
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switch(i.opsize)
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{
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case 2:
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v = t.read_i16(addr);
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break;
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case 4:
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v = t.read_i32(addr);
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break;
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default:
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throw std::runtime_error("Wrong pcrel opsize");
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}
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ca.value = DataValue(IntegerType::u32);
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2020-02-15 18:42:14 +01:00
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ca.value.write(0, 4, v);
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2020-02-12 07:53:00 +01:00
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}
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else if(a.kind == Argument::PcJump)
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{
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2020-02-12 16:33:08 +01:00
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uint32_t addr = pc + 4 + a.disp;
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ca.location = RelConstDomain().constant(addr);
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2020-02-15 18:42:14 +01:00
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ca.value = DataValue(IntegerType::u32);
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ca.value.write(0, 4, addr);
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2020-02-12 07:53:00 +01:00
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}
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}
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2019-12-28 17:18:13 +01:00
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enqueue_unseen_successors(pc, ci);
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}
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} /* namespace FxOS */
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