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fxos: rename Instruction -> OldInstruction

This commit is contained in:
Lephenixnoir 2023-09-24 10:45:40 +02:00
parent 0c52cfca27
commit 9d7c87ac3d
Signed by: Lephenixnoir
GPG Key ID: 1BBA026E13FC0495
10 changed files with 27 additions and 27 deletions
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16
include/fxos/disassembly.h
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@ -59,12 +59,12 @@ struct Argument
};
/* A loaded and annotated instruction. */
struct Instruction
struct OldInstruction
{
/* Build from instruction, cannot be nullptr. */
Instruction(AsmInstruction const *inst);
OldInstruction(AsmInstruction const *inst);
/* Build from opcode, if instruction could not be decoded. */
Instruction(uint16_t opcode);
OldInstruction(uint16_t opcode);
/* What instruction this is. Note that this does not determine all the
properties below. Placement and delay slots greatly alter them.
@ -174,14 +174,14 @@ struct Disassembly
// Instruction information
std::map<uint32_t, Instruction> instructions;
std::map<uint32_t, OldInstruction> instructions;
/* Check whether an instruction is loaded at PC */
bool hasInstructionAt(uint32_t pc);
/* Find an instruction by address. If the instruction is not loaded,
returns nullptr, unless [allowDiscovery] is set, in which case it's
loaded normally. */
Instruction *getInstructionAt(uint32_t pc, bool allowDiscovery = false);
OldInstruction *getInstructionAt(uint32_t pc, bool allowDiscovery = false);
// Function information
@ -278,7 +278,7 @@ public:
bool analyzeAllInstructions();
/* Analyze a single instruction */
virtual bool analyzeInstruction(uint32_t pc, Instruction &ins) = 0;
virtual bool analyzeInstruction(uint32_t pc, OldInstruction &ins) = 0;
/* Analyze a function by following its CFG */
using FunctionPass::analyzeFunction;
@ -289,8 +289,8 @@ public:
/* For custom analysis functions: enqueue successors. The update variant
enqueues them even if they were already seen. */
void enqueueSuccessors(uint32_t pc, Instruction &ins);
void updateSuccessors(uint32_t pc, Instruction &ins);
void enqueueSuccessors(uint32_t pc, OldInstruction &ins);
void updateSuccessors(uint32_t pc, OldInstruction &ins);
private:
Queue<uint32_t> m_queue;

2
include/fxos/passes/cfg.h
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@ -54,7 +54,7 @@ class CfgPass: public InstructionPass
{
public:
CfgPass(Disassembly &disasm);
bool analyzeInstruction(uint32_t pc, Instruction &inst) override;
bool analyzeInstruction(uint32_t pc, OldInstruction &inst) override;
/* Explore a new function at the specified address. This method creates the
function if it doesn't exist yet, explores its CFG, and generates claims

2
include/fxos/passes/pcrel.h
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@ -28,7 +28,7 @@ class PcrelPass: public InstructionPass
{
public:
PcrelPass(Disassembly &disasm);
bool analyzeInstruction(uint32_t pc, Instruction &inst) override;
bool analyzeInstruction(uint32_t pc, OldInstruction &inst) override;
};
} /* namespace FxOS */

2
include/fxos/passes/print.h
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@ -48,7 +48,7 @@ class PrintPass: public InstructionPass
{
public:
PrintPass(Disassembly &disasm);
bool analyzeInstruction(uint32_t pc, Instruction &inst) override;
bool analyzeInstruction(uint32_t pc, OldInstruction &inst) override;
//---
// Print pass parameters

2
include/fxos/passes/syscall.h
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@ -23,7 +23,7 @@ class SyscallPass: public InstructionPass
{
public:
SyscallPass(Disassembly &disasm, OS *os);
bool analyzeInstruction(uint32_t pc, Instruction &inst) override;
bool analyzeInstruction(uint32_t pc, OldInstruction &inst) override;
private:
OS *m_os;

16
lib/disassembly.cpp
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@ -38,14 +38,14 @@ Argument::Argument()
syscall_id = -1;
}
Instruction::Instruction(AsmInstruction const *inst):
OldInstruction::OldInstruction(AsmInstruction const *inst):
inst {inst}, args {}, opcode {inst->opcode}, leader {false},
delayslot {false}, terminal {false}, jump {false}, condjump {false},
jmptarget {0xffffffff}
{
}
Instruction::Instruction(uint16_t opcode):
OldInstruction::OldInstruction(uint16_t opcode):
inst {nullptr}, args {}, opcode {opcode}, leader {false}, delayslot {false},
terminal {false}, jump {false}, condjump {false}, jmptarget {0xffffffff}
{
@ -113,7 +113,7 @@ bool Disassembly::hasInstructionAt(uint32_t pc)
return this->instructions.count(pc) > 0;
}
Instruction *Disassembly::getInstructionAt(uint32_t pc, bool allowDiscovery)
OldInstruction *Disassembly::getInstructionAt(uint32_t pc, bool allowDiscovery)
{
if(pc & 1) {
FxOS_log(ERR, "reading instruction for disassembly at 0x%08x", pc);
@ -125,10 +125,10 @@ Instruction *Disassembly::getInstructionAt(uint32_t pc, bool allowDiscovery)
}
else if(allowDiscovery) {
uint16_t opcode = this->vspace.read_u16(pc);
Instruction i(opcode);
OldInstruction i(opcode);
if(insmap[opcode])
i = Instruction(&*insmap[opcode]);
i = OldInstruction(&*insmap[opcode]);
this->instructions.emplace(pc, i);
return &this->instructions.at(pc);
@ -349,7 +349,7 @@ bool InstructionPass::analyzeAnonymousFunction(uint32_t pc)
while(!m_queue.empty()) {
uint32_t pc = m_queue.pop();
Instruction *i = m_disasm.getInstructionAt(pc, m_allowDiscovery);
OldInstruction *i = m_disasm.getInstructionAt(pc, m_allowDiscovery);
if(i != nullptr && this->analyzeInstruction(pc, *i))
this->enqueueSuccessors(pc, *i);
@ -360,7 +360,7 @@ bool InstructionPass::analyzeAnonymousFunction(uint32_t pc)
return ok;
}
void InstructionPass::enqueueSuccessors(uint32_t pc, Instruction &i)
void InstructionPass::enqueueSuccessors(uint32_t pc, OldInstruction &i)
{
if(!i.terminal && !i.jump)
m_queue.enqueue(pc + 2);
@ -368,7 +368,7 @@ void InstructionPass::enqueueSuccessors(uint32_t pc, Instruction &i)
m_queue.enqueue(i.jmptarget);
}
void InstructionPass::updateSuccessors(uint32_t pc, Instruction &i)
void InstructionPass::updateSuccessors(uint32_t pc, OldInstruction &i)
{
if(!i.terminal && !i.jump)
m_queue.update(pc + 2);

8
lib/passes/cfg.cpp
View File

@ -18,7 +18,7 @@ CfgPass::CfgPass(Disassembly &disasm):
this->setAllowDiscovery(true);
}
bool CfgPass::analyzeInstruction(uint32_t pc, Instruction &i)
bool CfgPass::analyzeInstruction(uint32_t pc, OldInstruction &i)
{
/* Don't explore successors if the instruction cannot be decoded, not
even pc+2. This will prevent wild overshoot. */
@ -45,7 +45,7 @@ bool CfgPass::analyzeInstruction(uint32_t pc, Instruction &i)
jmptarget = (pc + 4) + args[0].disp;
/* Make the target of the jump a leader */
Instruction &target = *m_disasm.getInstructionAt(jmptarget, true);
OldInstruction &target = *m_disasm.getInstructionAt(jmptarget, true);
target.leader = true;
/* Check that it's not in a delay slot */
@ -68,7 +68,7 @@ bool CfgPass::analyzeInstruction(uint32_t pc, Instruction &i)
}
/* If it has a delay slot, create it at the next instruction */
else if(i.inst->hasDelaySlot()) {
Instruction &slot = *m_disasm.getInstructionAt(pc + 2, true);
OldInstruction &slot = *m_disasm.getInstructionAt(pc + 2, true);
if(slot.leader)
throw std::logic_error(format(
"0x%08x is a leader and also a delay"
@ -111,7 +111,7 @@ bool CfgPass::exploreFunction(uint32_t pc)
/* Look for call targets */
for(uint32_t pc: m_claimedInstructions) {
Instruction const *ci = m_disasm.getInstructionAt(pc);
OldInstruction const *ci = m_disasm.getInstructionAt(pc);
if(!ci)
continue;
AsmInstruction const &i = *ci->inst;

2
lib/passes/pcrel.cpp
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@ -14,7 +14,7 @@ PcrelPass::PcrelPass(Disassembly &disasm): InstructionPass(disasm)
{
}
bool PcrelPass::analyzeInstruction(uint32_t pc, Instruction &ci)
bool PcrelPass::analyzeInstruction(uint32_t pc, OldInstruction &ci)
{
AsmInstruction const *i = ci.inst;
if(!i)

2
lib/passes/print.cpp
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@ -26,7 +26,7 @@ PrintPass::PrintPass(Disassembly &disasm):
m_symtables.push_back(disasm.vspace.symbols);
}
bool PrintPass::analyzeInstruction(uint32_t pc, Instruction &i)
bool PrintPass::analyzeInstruction(uint32_t pc, OldInstruction &i)
{
/* Ellipsis if there is a gap since last instruction */

2
lib/passes/syscall.cpp
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@ -14,7 +14,7 @@ SyscallPass::SyscallPass(Disassembly &disasm, OS *os):
{
}
bool SyscallPass::analyzeInstruction(uint32_t pc, Instruction &ci)
bool SyscallPass::analyzeInstruction(uint32_t pc, OldInstruction &ci)
{
/* Nothing to do if no syscall table is provided! */
if(!m_os)