67 lines
2.4 KiB
C++
67 lines
2.4 KiB
C++
//---------------------------------------------------------------------------//
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// 1100101 |_ mov #0, r4 __ //
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// 11 |_ <0xb380 %5c4> / _|_ _____ ___ //
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// 0110 |_ 3.50 -> 3.60 | _\ \ / _ (_-< //
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// |_ base# + offset |_| /_\_\___/__/ //
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//---------------------------------------------------------------------------//
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#include <fxos/passes/pcrel.h>
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#include <fxos/vspace.h>
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namespace FxOS {
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PcrelPass::PcrelPass(Disassembly &disasm): InstructionPass(disasm)
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{
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}
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bool PcrelPass::analyzeInstruction(uint32_t pc, Instruction &ci)
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{
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AsmInstruction const *i = ci.inst;
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if(!i)
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return true;
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for(size_t n = 0; n < i->arg_count; n++) {
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AsmArgument const &arg = i->args[n];
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Argument &a = ci.args[n];
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if(arg.kind == AsmArgument::PcRel
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&& (i->opsize == 2 || i->opsize == 4)) {
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uint32_t addr = (pc & ~(arg.opsize - 1)) + 4 + arg.disp;
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a.location = RelConstDomain().constant(addr);
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/* Also compute the value. This is sign-extended from 16-bit with
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mov.w. There is no mov.b for this instruction. */
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VirtualSpace &space = m_disasm.vspace;
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uint32_t v = -1;
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if(i->opsize == 2 && space.covers(addr, 2)) {
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v = space.read_i16(addr);
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a.value = RelConstDomain().constant(v);
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}
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if(i->opsize == 4 && space.covers(addr, 4)) {
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v = space.read_i32(addr);
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a.value = RelConstDomain().constant(v);
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}
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}
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else if(arg.kind == AsmArgument::PcJump) {
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uint32_t addr = pc + 4 + arg.disp;
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a.location = RelConstDomain().constant(addr);
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a.value = RelConstDomain().constant(addr);
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}
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else if(arg.kind == AsmArgument::PcAddr) {
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uint32_t addr = (pc & ~3) + 4 + arg.disp;
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/* SH3 manual says that mova uses the target address of the jump
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when in a delay slot. SH4AL-DSP makes it invalid. */
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// if(ci.delayslot) addr = (ci.jmptarget & ~3) + 4 + a.disp;
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a.location = RelConstDomain().constant(addr);
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a.value = RelConstDomain().constant(addr);
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}
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}
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return true;
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}
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} /* namespace FxOS */
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