81 lines
2.0 KiB
C++
81 lines
2.0 KiB
C++
//---
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// fxos.passes.cfg: Control Flow Graph construction
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//---
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#include <fxos/disasm-passes/cfg.h>
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#include <fxos/disassembly.h>
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#include <fxos/errors.h>
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#include <fxos/log.h>
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#include <cassert>
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using namespace FxOS::Log;
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namespace FxOS {
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CfgPass::CfgPass(Disassembly &disasm):
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DisassemblyPass(disasm)
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{
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}
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void CfgPass::analyze(uint32_t pc, ConcreteInstruction &ci)
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{
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/* Compute the jump target for jump instructions. This is easy because
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they are all trivially computable. (...If they are not we dub them
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"terminal" to avoid the computation!) */
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uint32_t jmptarget = 0xffffffff;
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if(ci.inst.isjump() || ci.inst.iscondjump())
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{
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auto &args = ci.inst.args;
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if(args.size() != 1 || args[0].kind != Argument::PcJump)
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throw LangError(pc, "invalid jump instruction");
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jmptarget = (pc+4) + args[0].disp;
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/* Make the target of the jump a leader */
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ConcreteInstruction &target = m_disasm.readins(jmptarget);
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target.leader = true;
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/* Check that it's not in a delay slot */
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if(target.delayslot)
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throw LangError(pc, "jump into a delay slot!");
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}
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/* If this instruction is in a delay slot, check its type. A valid
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delay slot has no branching properties on its own, so nothing new to
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set in the properties. */
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if(ci.delayslot)
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{
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if(!ci.inst.isvaliddelayslot())
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throw LangError(pc, "invalid delay slot");
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}
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/* Handle normal instructions */
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else if(!ci.inst.isdelayed())
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{
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ci.terminal = ci.inst.isterminal();
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ci.jump = ci.inst.isjump();
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ci.condjump = ci.inst.iscondjump();
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ci.jmptarget = jmptarget;
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}
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/* Create a new delay slot */
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else
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{
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ConcreteInstruction &slot = m_disasm.readins(pc+2);
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if(slot.leader)
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throw LangError(pc+2, "leader in a delay slot!");
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if(!slot.inst.isvaliddelayslot())
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throw LangError(pc+2, "invalid delay slot");
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slot.delayslot = true;
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slot.terminal = ci.inst.isterminal();
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slot.jump = ci.inst.isjump();
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slot.condjump = ci.inst.iscondjump();
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slot.jmptarget = jmptarget;
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}
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enqueue_unseen_successors(pc, ci);
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}
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} /* namespace FxOS */
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