412 lines
12 KiB
C++
412 lines
12 KiB
C++
//---------------------------------------------------------------------------//
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// 1100101 |_ mov #0, r4 __ //
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// 11 |_ <0xb380 %5c4> / _|_ _____ ___ //
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// 0110 |_ 3.50 -> 3.60 | _\ \ / _ (_-< //
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// |_ base# + offset |_| /_\_\___/__/ //
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//---------------------------------------------------------------------------//
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// fxos/lang: Assembler language syntax
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//
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// This file defines the syntactic tools needed to read and manipulate
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// assembler instructions.
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//
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// The CpuRegister class is a glorified type-safe enumeration. Registers can be
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// named, fi. CpuRegister::R0; they can be constructed from their lowercase
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// name as a string, fi. CpuRegister("r0"); and they can be printed with the
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// .str() method.
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//
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// The Argument struct represents an argument to an instruction. This is
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// syntactic only; for instance Deref (@rn) does not mean that memory is
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// accessed, since [jmp @rn] or [ocbwb @rn] do not actually access @rn.
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// Constructor functions such as Argument_Deref() are provided.
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//
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// Finally, the Instruction struct represents an abstract instruction out of
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// context. Each Instruction object only models one particular instance of one
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// particular instruction, for instance [mov #14, r2] and not [mov #imm, rn].
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// The rationale for this is disassembly speed and a number of simplifications
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// for passes; and there are less than 65'000 non-DSP instructions anyway.
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//---
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#ifndef FXOS_LANG_H
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#define FXOS_LANG_H
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#include <fxos/util/types.h>
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#include <cassert>
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#include <ranges>
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#include <string>
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#include <array>
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namespace FxOS {
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/* CPU register names, with a little meat for conversion to and from string */
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class CpuRegister
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{
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public:
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// clang-format off
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enum CpuRegisterName: i8 {
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/* Value 0 is reserved for special purposes such as "no register" */
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UNDEFINED = 0,
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/* Caller-saved general-purpose registers */
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R0, R1, R2, R3, R4, R5, R6, R7,
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/* Banked general-purpose registers. fxos does not account for
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banking identities, these are just for naming and output. */
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R0B, R1B, R2B, R3B, R4B, R5B, R6B, R7B,
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/* Callee-saved general-purpose registers */
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R8, R9, R10, R11, R12, R13, R14, R15,
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/* System registers */
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MACH, MACL, PR, PC,
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/* Control registers */
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SR, SSR, SPC, GBR, VBR, DBR, SGR,
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};
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// clang-format on
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CpuRegister() = default;
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/* Construction from CpuRegisterName */
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constexpr CpuRegister(CpuRegisterName name): m_name(name)
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{
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}
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/* Construction from string */
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CpuRegister(std::string register_name);
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/* Conversion to string */
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std::string str() const noexcept;
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/* Conversion to CpuRegisterName for switch statements */
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constexpr operator CpuRegisterName() noexcept
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{
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return m_name;
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}
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/* Comparison operators */
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constexpr bool operator==(CpuRegister r) const
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{
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return m_name == r.m_name;
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}
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constexpr bool operator!=(CpuRegister r) const
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{
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return m_name != r.m_name;
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}
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/* Get the register number for r0 ... r15, -1 for other registers. */
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int getRn() const;
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/* Make an r0 ... r15 register name from its number. */
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static CpuRegister makeRn(int n);
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private:
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CpuRegisterName m_name;
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};
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/* Operands to raw assembler instructions */
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struct AsmOperand
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{
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enum Kind : i8 {
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Reg, /* rn */
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Deref, /* @rn */
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PostInc, /* @rn+ */
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PreDec, /* @-rn */
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StructDeref, /* @(disp,rn) or @(disp,gbr) */
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ArrayDeref, /* @(r0,rn) or @(r0,gbr) */
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PcRel, /* @(disp,pc) with 4-alignment correction */
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PcJump, /* pc+disp */
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PcAddr, /* pc+disp (the address itself, for mova) */
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Imm, /* #imm */
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};
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/* Default constructor gives register r0. */
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AsmOperand();
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/* Factory functions */
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static AsmOperand mkReg(CpuRegister base)
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{
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return AsmOperand(Reg, base, 0);
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}
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static AsmOperand mkDeref(CpuRegister base, i8 opsize)
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{
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return AsmOperand(Deref, base, opsize);
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}
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static AsmOperand mkPostInc(CpuRegister base, i8 opsize)
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{
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return AsmOperand(PostInc, base, opsize);
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}
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static AsmOperand mkPreDec(CpuRegister base, i8 opsize)
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{
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return AsmOperand(PreDec, base, opsize);
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}
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static AsmOperand mkStructDeref(int disp, int opsize, CpuRegister base)
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{
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return AsmOperand(disp, opsize, base);
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}
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static AsmOperand mkArrayDeref(
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CpuRegister index, CpuRegister base, i8 opsize)
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{
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return AsmOperand(index, base, opsize);
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}
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static AsmOperand mkPcRel(int disp, int opsize)
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{
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return AsmOperand(PcRel, disp, opsize);
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}
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static AsmOperand mkPcJump(int disp)
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{
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return AsmOperand(PcJump, disp);
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}
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static AsmOperand mkPcAddr(int disp)
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{
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return AsmOperand(PcAddr, disp);
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}
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static AsmOperand mkImm(int imm)
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{
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return AsmOperand(Imm, imm);
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}
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std::string str() const;
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/* Is this operand a register? */
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bool isRegister() const
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{
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return m_kind == Reg;
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}
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/* Is this operand in memory? */
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bool isMemory() const
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{
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switch(m_kind) {
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case Deref:
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case PostInc:
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case PreDec:
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case StructDeref:
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case ArrayDeref:
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case PcRel:
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return true;
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case Reg:
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case PcJump:
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case PcAddr:
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case Imm:
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return false;
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}
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return false;
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}
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/* Is this operand a constant? */
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bool isConstant() const
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{
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switch(m_kind) {
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case PcRel:
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case PcJump:
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case PcAddr:
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case Imm:
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return true;
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case Reg:
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case Deref:
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case PostInc:
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case PreDec:
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case StructDeref:
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case ArrayDeref:
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return false;
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}
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return false;
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}
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// TODO: RelConst modeling the memory address being being used (first
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// without current state, then with it, for r0/rn, disp/pc, and r0/gbr)
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Kind kind() const
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{
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return m_kind;
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}
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CpuRegister base() const
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{
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assert(m_kind != Imm && "invalid AsmOperand accessor: base");
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return m_base;
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}
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CpuRegister index() const
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{
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assert(m_kind == ArrayDeref && "invalid AsmOperand accessor: index");
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return m_index;
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}
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int opsize() const
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{
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return m_opsize;
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}
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int disp() const
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{
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assert((m_kind == StructDeref || m_kind == PcRel || m_kind == PcJump
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|| m_kind == PcAddr)
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&& "invalid AsmOperand accessor: disp");
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return m_disp_imm;
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}
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int imm() const
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{
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assert(m_kind == Imm && "invalid AsmOperand accessor: imm");
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return m_disp_imm;
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}
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/* Is this operand computed using a PC-relative address? */
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bool usesPCRelativeAddressing() const
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{
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return m_kind == PcRel || m_kind == PcJump || m_kind == PcAddr;
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}
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/* Get the PC-relative target, assuming the instruction is at the provided
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address, for arguments with PC-relative adressing. */
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u32 getPCRelativeTarget(u32 pc) const;
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private:
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AsmOperand(Kind kind, CpuRegister base, i8 opsize);
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AsmOperand(int disp, i8 opsize, CpuRegister base);
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AsmOperand(CpuRegister index, CpuRegister base, i8 opsize);
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AsmOperand(Kind kind, int disp_imm, i8 opsize = 0);
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Kind m_kind;
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/* Base register. Valid for all modes except Imm */
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CpuRegister m_base;
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/* Index register. Valid for ArrayDeref */
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CpuRegister m_index;
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/* Operation size (0, 1, 2 or 4). Generally a multiplier for disp */
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i8 m_opsize;
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/* Displacement in bytes for StructDeref, PcRel, PcJump, and PcAddr, or
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immediate value for Imm. */
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int m_disp_imm;
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};
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/* Assembler instruction */
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struct AsmInstruction
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{
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enum Tag {
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IsReturn = 0x01,
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IsUnconditionalJump = 0x02,
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IsConditionalJump = 0x04,
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IsCall = 0x08,
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HasDelaySlot = 0x10,
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IsInvalidDelaySlot = 0x20,
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IsDynamicJump = 0x40,
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};
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#define GENDEFS_INSN(NAME, STR) SH_##NAME,
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enum {
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#include "gendefs/insn.h"
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SH_MAX,
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};
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#undef GENDEFS_INSN
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static_assert(SH_MAX <= 0xff);
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AsmInstruction(u32 encoding, char const *mnemonic, int tags, int opCount,
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AsmOperand op1 = {}, AsmOperand op2 = {});
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/* Operation code, one of AsmInstruction::SH_* (eg. SH_mov) */
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uint operation() const
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{
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return m_operation;
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}
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/* Access to operands */
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int operandCount() const
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{
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return m_opCount;
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}
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AsmOperand const &operand(int i) const
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{
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assert((uint)i < m_opCount && "operand out-of-bounds");
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return m_ops[i];
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}
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auto operands() const // -> [AsmOperand const &]
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{
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return std::views::take(m_ops, m_opCount);
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}
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/* Size indication (purely syntactic), 0 if not present */
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int opsize() const
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{
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return m_opsize;
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}
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/* Original encoding */
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u32 encoding() const
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{
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return m_encoding;
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}
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/* Mnemonic (with the size indicator, eg. "mov.l") */
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std::string mnemonic() const;
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/* Operation name (without the size indicator, eg. "mov") */
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char const *operationString() const;
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/* Size indicator to go after the op name (".b", ".w", ".l" or empty) */
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char const *operationSizeString() const;
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//=== Instruction classes ===//
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/* Whether the instruction terminates the function it's in. */
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bool isReturn() const
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{
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return (m_tags & Tag::IsReturn) != 0;
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}
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/* Whether the instruction is a conditional/unconditional static jump. */
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bool isConditionalJump() const
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{
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return (m_tags & Tag::IsConditionalJump) != 0;
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}
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bool isUnconditionalJump() const
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{
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return (m_tags & Tag::IsUnconditionalJump) != 0;
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}
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bool isAnyStaticJump() const
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{
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int IsJump = Tag::IsConditionalJump | Tag::IsUnconditionalJump;
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return (m_tags & IsJump) != 0;
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}
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/* Whether the instruction jumps to a dynamic target. This does not include
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*calls* to dynamic targets. These jumps are always unconditional. */
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bool isDynamicJump() const
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{
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return (m_tags & Tag::IsDynamicJump) != 0;
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}
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/* Whether the instruction is a function call. */
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bool isCall() const
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{
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return (m_tags & Tag::IsCall) != 0;
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}
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/* Whether the instruction has a delay slot */
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bool hasDelaySlot() const
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{
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return (m_tags & Tag::HasDelaySlot) != 0;
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}
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/* Wheher the instruction terminates its basic block. */
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bool isBlockTerminator() const
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{
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return isAnyStaticJump() || isDynamicJump() || isReturn();
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}
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/* Whether the instruction can be used in a delay slot. */
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bool isValidDelaySlot() const
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{
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return !isBlockTerminator() && !hasDelaySlot()
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&& (m_tags & Tag::IsInvalidDelaySlot) == 0;
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}
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//=== Instruction info ===//
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/* Get the PC-relative target, assuming the instruction is at the provided
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address, for instructions with PC-relative offsets. */
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u32 getPCRelativeTarget(u32 pc) const;
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private:
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/* Original encoding */
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u32 m_encoding;
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/* Assembler instruction name (mov, add, etc), without size modifier. */
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u8 m_operation;
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/* Operation size (0, 1, 2 or 4) */
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i8 m_opsize;
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/* Number of operands */
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u8 m_opCount;
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/* Instruction tags */
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u16 m_tags;
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/* Operands */
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std::array<AsmOperand, 2> m_ops;
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};
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} /* namespace FxOS */
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#endif /* FXOS_LANG_H */
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