67 lines
1.6 KiB
C++
67 lines
1.6 KiB
C++
//---
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// fxos.passes.pcrel: Resolution of PC-relative addresses
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//---
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#include <fxos/disasm-passes/pcrel.h>
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namespace FxOS {
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PcrelPass::PcrelPass(Disassembly &disasm):
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InstructionDisassemblyPass(disasm, "pcrel")
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{
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}
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void PcrelPass::analyze(uint32_t pc, ConcreteInstruction &ci)
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{
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Instruction const *i = ci.inst;
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if(!i) return;
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for(size_t n = 0; n < i->arg_count; n++)
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{
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Argument const &a = i->args[n];
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ConcreteInstructionArg &ca = ci.args[n];
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if(a.kind == Argument::PcRel &&
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(i->opsize == 2 || i->opsize == 4))
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{
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uint32_t addr = (pc & ~(a.opsize - 1)) + 4 + a.disp;
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ca.location = RelConstDomain().constant(addr);
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/* Also compute the value. This is sign-extended from
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16-bit with mov.w. There is no mov.b for this
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instruction. */
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Target &t = m_disasm.target();
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uint32_t v = -1;
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if(i->opsize == 2) v = t.read_i16(addr);
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if(i->opsize == 4) v = t.read_i32(addr);
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ca.value = DataValue(IntegerType::u32);
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ca.value.write(0, 4, v);
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}
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else if(a.kind == Argument::PcJump)
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{
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uint32_t addr = pc + 4 + a.disp;
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ca.location = RelConstDomain().constant(addr);
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ca.value = DataValue(IntegerType::u32);
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ca.value.write(0, 4, addr);
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}
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else if(a.kind == Argument::PcAddr
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&& m_disasm.passes.count("cfg"))
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{
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uint32_t addr = (pc & ~3) + 4 + a.disp;
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/* SH3 manual says that the semantics of mova change in
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a delay slot. GNU as: "yeah but sorry they don't" */
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// if(ci.delayslot) addr = (ci.jmptarget&~3) + 4 + a.disp;
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ca.location = RelConstDomain().constant(addr);
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ca.value = DataValue(IntegerType::u32);
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ca.value.write(0, 4, addr);
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}
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}
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}
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} /* namespace FxOS */
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