137 lines
3.3 KiB
C++
137 lines
3.3 KiB
C++
//---
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// fxos.lang: Assembler language specification
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//---
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#ifndef LIBFXOS_LANG_H
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#define LIBFXOS_LANG_H
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#include <string>
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#include <vector>
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#include <cstdint>
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namespace FxOS {
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/* CPU register names, with a little meat for conversion to and from string */
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class CpuRegister
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{
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public:
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enum CpuRegisterName {
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/* Caller-saved general-purpose registers */
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R0, R1, R2, R3, R4, R5, R6, R7,
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/* Banked general-purpose registers. fxos does not account for
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banking identities, these are just for naming and output. */
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R0B, R1B, R2B, R3B, R4B, R5B, R6B, R7B,
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/* Callee-saved general-purpose registers */
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R8, R9, R10, R11, R12, R13, R14, R15,
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/* System registers */
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MACH, MACL, PR, PC,
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/* Control registers */
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SR, SSR, SPC, GBR, VBR, DBR, SGR,
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};
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CpuRegister() = default;
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/* Construction from CpuRegisterName */
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constexpr CpuRegister(CpuRegisterName name): m_name(name) {}
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/* Construction from string */
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CpuRegister(std::string register_name);
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/* Conversion to string */
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std::string str() const noexcept;
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/* Conversion to CpuRegisterName for switch statements */
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constexpr operator CpuRegisterName() noexcept { return m_name; }
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/* Comparison operators */
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constexpr bool operator==(CpuRegister r) const {
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return m_name == r.m_name;
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}
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constexpr bool operator!=(CpuRegister r) const {
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return m_name != r.m_name;
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}
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private:
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CpuRegisterName m_name;
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};
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/* Addressing modes for arguments */
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struct Argument
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{
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/* Various addressing modes in the language */
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enum Kind {
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Reg, /* rn */
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Deref, /* @rn */
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PostInc, /* @rn+ */
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PreDec, /* @-rn */
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StructDeref, /* @(disp,rn) or @(disp,gbr) */
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ArrayDeref, /* @(r0,rn) or @(r0,gbr) */
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PcRel, /* @(disp,pc) with 4-alignment correction */
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PcJump, /* disp */
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Imm, /* #imm */
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};
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Argument() = default;
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/* String representation */
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std::string str() const;
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/* Addressing mode */
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Kind kind;
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/* Base register. Valid for all modes except Imm */
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CpuRegister base;
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/* Index register. Valid for ArrayDeref */
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CpuRegister index;
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/* Displacement in bytes. Valid for StructDeref, PcRel and PcJump */
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int disp;
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/* Operation size. Generally a multiplier for disp */
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int opsize;
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/* Immediate value. Valid for Imm */
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int imm;
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};
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/* Argument constructors */
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Argument Argument_Reg(CpuRegister base);
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Argument Argument_Deref(CpuRegister base);
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Argument Argument_PostInc(CpuRegister base);
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Argument Argument_PreDec(CpuRegister base);
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Argument Argument_StructDeref(int disp, int opsize, CpuRegister base);
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Argument Argument_ArrayDeref(CpuRegister index, CpuRegister base);
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Argument Argument_PcRel(int disp, int opsize);
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Argument Argument_PcJump(int disp);
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Argument Argument_Imm(int imm);
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/* Assembler instruction */
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struct Instruction
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{
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Instruction() = default;
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/* Construct with one or several arguments */
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Instruction(std::string mnemonic);
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Instruction(std::string mnemonic, Argument arg);
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Instruction(std::string mnemonic, Argument arg1, Argument arg2);
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/* Original opcode. Initialized to 0 when unset, which is an invalid
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instruction by design. */
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uint16_t opcode;
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/* Mnemonic **without the size indicator** */
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std::string mnemonic;
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/* Operation size (0, 1, 2 or 4) */
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int opsize;
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/* Arguments */
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std::vector<Argument> args;
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};
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} /* namespace FxOS */
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#endif /* LIBFXOS_LANG_H */
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