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gint/src/kernel/exch.s

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core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
.global _gint_exch
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
.section .gint.exch, "ax"
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
.align 4
core: answer TLB misses and remove startup mapping (UNSTABLE) This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
2020-06-14 18:22:20 +02:00
_gint_exch:
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
sts.l pr, @-r15
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
stc.l gbr, @-r15
sts.l mach, @-r15
sts.l macl, @-r15
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
mov.l r8, @-r15
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
mov.l r9, @-r15
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
/* Get the first word of the gint hardware array (HWMPU). If it has the
last bit set, we're SH3 */
mov.l .gint, r0
mov.l @r0, r0
tst #1, r0
mov.l .expevt_sh4, r8
bt catch
mov.l .expevt_sh3, r8
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
catch:
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
/* Panic if the catcher is NULL */
mov.l .catcher, r0
mov.l @r0, r0
tst r0, r0
bt panic
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
/* Set BL=0, IMASK=15 */
stc sr, r9
mov.l .SR_set_IMASK, r1
or r9, r1
mov.l .SR_clear_BL, r2
and r2, r1
ldc r1, sr
/* Call the catcher and leave if it returns zero (exception handled) */
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
jsr @r0
mov.l @r8, r4
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
ldc r9, sr
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
tst r0, r0
bt end
panic:
/* RTE to the panic function, but manually, so that SPC is preserved */
mov.l @r8, r4
ldc r4, r4_bank
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
mov.l @r15+, r9
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
mov.l @r15+, r8
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
lds.l @r15+, macl
lds.l @r15+, mach
ldc.l @r15+, gbr
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
lds.l @r15+, pr
/* Here we switch banks so r0..r7 change meaning! */
stc ssr, r0
ldc r0, sr
mov.l .panic, r0
mov.l @r0, r0
jmp @r0
nop
end:
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
mov.l @r15+, r9
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
mov.l @r15+, r8
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
lds.l @r15+, macl
lds.l @r15+, mach
ldc.l @r15+, gbr
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
lds.l @r15+, pr
rte
nop
.align 4
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
.gint:
.long _gint
.expevt_sh4:
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
.long 0xff000024
periodic check of SH3 compatibility
2020-05-31 22:26:30 +02:00
.expevt_sh3:
.long 0xffffffd4
core: allow custom panics and exception catching This change introduces two new mechanismes for executing user code when an exception occurs. * This first is the custom panic message, which usually displays "System ERROR". The function that performs this task can now be user-defined. It is also run in user mode because the exception handler rte's into it, allowing it to execute any kind of interrupt-inducing task. The behavior is undefined if this function raises an exception. * The second is an exception-catching function, which (when set) is called every time an exception occurs, and is granted the chance of handling the exception to continue execution normally. It can be used in various ways, the most primitive of which is recording the exception and going back. It runs in interrupt mode and must not raise any kind of exception.
2019-09-13 08:10:30 +02:00
.catcher:
.long _gint_exc_catcher
.panic:
.long _gint_exc_panic
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
.SR_set_IMASK:
.long (0xf << 4)
.SR_clear_BL:
.long ~(1 << 28)