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gint/src/kernel/cpu.h

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some cleanup in src/core and in the repository
2020-06-20 11:41:13 +02:00
//---
// core:cpu - CPU registers and operation management
//---
#ifndef GINT_CORE_CPU
#define GINT_CORE_CPU
#include <gint/defs/types.h>
/* cpu_setVBR(): Change VBR address
Blocks interrupts then changes the VBR address and calls the provided INTC
configuration function before restoring interrupts. This function must
configure the INTC in a way that is safe for the new VBR controller,
including disabling all interrupts that it cannot handle.
kernel: dynamic loading of GMAPPED functions to user RAM This commit introduces a large architectural change. Unlike previous models of the fx-9860G series, the G-III models have a new user RAM address different from 8801c000. The purpose of this change is to dynamically load GMAPPED functions to this address by querying the TLB, and call them through a function pointer whose address is determined when loading. Because of the overhead of using a function pointer in both assembly and C code, changes have been made to avoid GMAPPED functions altogether. Current, only cpu_setVBR() and gint_inth_callback() are left, the second being used specifically to enable TLB misses when needed. * Add a .gint.mappedrel section for the function pointers holding addresses to GMAPPED functions; add function pointers for cpu_setVBR() and gint_inth_callback() * Move rram to address 0 instead of the hardcoded 0x8801c000 * Load GMAPPED functions at their linked address + the physical address user RAM is mapped, to and compute their function pointers * Remove the GMAPPED macro since no user function needs it anymore * Add section flags "ax" (code) or "aw" (data) to every custom .section in assembler code, as they default to unpredictable values that can cause the section to be marked NOLOAD by the linker * Update the main kernel, TMU, ETMU and RTC interrupt handlers to use the new indirect calling method This is made possible by new MMU functions giving direct access to the physical area behind any virtualized page. * Add an mmu_translate() function to query the TLB * Add an mmu_uram() function to access user RAM from P1 The exception catching mechanism has been modified to avoid the use of GMAPPED functions altogether. * Set SR.BL=0 and SR.IMASK=15 before calling exception catchers * Move gint_exc_skip() to normal text ROM * Also fix registers not being popped off the stack before a panic The timer drivers have also been modified to avoid GMAPPED functions. * Invoke timer_stop() through gint_inth_callback() and move it to ROM * Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4) * Remove the timer_clear() function by inlining it into the ETMU handler (TCR is provided within the storage block of each timer) * Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s Additionally, VBR addresses are now determined at runtime to further reduce hardcoded memory layout addresses in the linker script. * Determine fx-9860G VBR addresses dynamically from mmu_uram() * Determine fx-CG 50 VBR addresses dynamically from mmu_uram() * Remove linker symbols for VBR addresses Comments and documentation have been updated throughout the code to reflect the changes.
2020-09-17 14:48:54 +02:00
This function is loaded to a platform-dependent address determined at
runtime; call it indirectly through the function pointer.
some cleanup in src/core and in the repository
2020-06-20 11:41:13 +02:00
@vbr New VBR address
@conf_intc Configuration function
general cleanup of the kernel * Removed .pretext sections since the TLB is now entirely dynamic; left only .text.entry for the start symbol. * Reworked the main files of src/core to move the INTC to its own driver and let the kernel handle only VBR space and CPU (now: VBR & CPUOPM). * Moved src/core/gint.c to src/core/kernel.c and centralized all driver loops that save or restore context for more robustness. This leaves the callbacks of cpu_setVBR() (formerly gint_setvbr()) pretty short. * Coalesced gint_switch_out() and gint_switch_in() into a single function callback for cpu_setVBR(). * Added an abstraction of interrupt signals as an enumerated value so that drivers no longer hardcode the IPR and IMR numbers and bits, sometimes even with isSH3() due to differences in the SH7705. * Changed the interrupt blocking method in cpu_setVBR() from SR.BL=1 to SR.IMASK=15 so that TLB misses are still handled. This removes the need for callback functions to be GMAPPED. * Moved gint_osmenu() and its utilities to a new file src/core/osmenu.c.
2020-06-20 17:18:51 +02:00
@arg Additional argument for conf_intc
some cleanup in src/core and in the repository
2020-06-20 11:41:13 +02:00
Returns the previous VBR address. */
kernel: do not rely on COMMON sections for GMAPPED refs Seems to break with binutils 2.35.
2020-09-22 15:17:31 +02:00
extern uint32_t (*cpu_setVBR)(uint32_t vbr, void (*conf_intc)(int arg),
int arg);
some cleanup in src/core and in the repository
2020-06-20 11:41:13 +02:00
/* cpu_setCPUOPM(): Change the CPU Operation Mode register
Updates the CPU Operation Mode with the specified settings, then performs a
read and an ICBI to register the change. Only writable bits of CPUOPM should
be changed, other bits must be left at the value given by cpu_getcpuopm().
@CPUOPM New operation mode */
void cpu_setCPUOPM(uint32_t CPUOPM);
/* cpu_getCPUOPM(): Get the CPU OperatioN Mode register */
uint32_t cpu_getCPUOPM(void);
#endif /* GINT_CORE_CPU */