pfc: add the SH7305 PFC description
Co-authored-by: Slyvtt <pillot.sylvain@gmail.com>
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1BBA026E13FC0495
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@ -76,9 +76,161 @@ typedef volatile struct
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#define SH7705_PFC (*((sh7705_pfc_t *)0xa4000100))
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//---
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// TODO: Document the SH7305 Pin Function Controller
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// SH7305 Pin Function Controller.
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// This is somewhat reminiscent of the SH7724, but there are many differences.
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// The official emulator is the basis for this module, with extra registers
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// added based on known differences with actual hardware (eg. few last ports).
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//---
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/* All port control registers (PCRx) have 2-bit entries specifying 4 pin modes:
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00: Special functions
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01: Output
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10: Input (pull-up ON)
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11: Input (pull-up OFF)
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Some pins do not accept all settings. The SH7724 has these exceptions:
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- PGCR (all pins): Input now allowed (00 and 01 only)
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- PJCR.P5MD/P6MD/P7MD: Input not allowed (00 and 01 only)
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Also, some entries are not configurable or are not mapped to actual pins.
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Again the SH7724 has these exceptions:
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- PGCR.P6MD/P7MD: No setting
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- PJCR.P4MD: No setting
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- PSCR.P7MD: No setting */
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typedef volatile word_union(sh7305_pfc_control_t,
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uint16_t P7MD :2;
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uint16_t P6MD :2;
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uint16_t P5MD :2;
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uint16_t P4MD :2;
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uint16_t P3MD :2;
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uint16_t P2MD :2;
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uint16_t P1MD :2;
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uint16_t P0MD :2;
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);
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/* Data register; a plain 8-bit value. Each bit can be either read or written
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depending on the mode of the corresponding pin. */
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typedef volatile byte_union(sh7305_pfc_data_t,
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uint8_t P7DT :1;
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uint8_t P6DT :1;
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uint8_t P5DT :1;
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uint8_t P4DT :1;
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uint8_t P3DT :1;
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uint8_t P2DT :1;
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uint8_t P1DT :1;
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uint8_t P0DT :1;
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);
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typedef volatile struct
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{
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sh7305_pfc_control_t
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PACR, PBCR, PCCR, PDCR, PECR, PFCR, PGCR, PHCR,
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PJCR, PKCR, PLCR, PMCR, PNCR, PQCR, PRCR, PSCR;
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sh7305_pfc_data_t PADR;
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pad(1);
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sh7305_pfc_data_t PBDR;
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pad(1);
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sh7305_pfc_data_t PCDR;
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pad(1);
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sh7305_pfc_data_t PDDR;
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pad(1);
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sh7305_pfc_data_t PEDR;
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pad(1);
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sh7305_pfc_data_t PFDR;
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pad(1);
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sh7305_pfc_data_t PGDR;
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pad(1);
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sh7305_pfc_data_t PHDR;
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pad(1);
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sh7305_pfc_data_t PJDR;
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pad(1);
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sh7305_pfc_data_t PKDR;
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pad(1);
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sh7305_pfc_data_t PLDR;
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pad(1);
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sh7305_pfc_data_t PMDR;
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pad(1);
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sh7305_pfc_data_t PNDR;
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pad(1);
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sh7305_pfc_data_t PQDR;
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pad(1);
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sh7305_pfc_data_t PRDR;
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pad(1);
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sh7305_pfc_data_t PSDR;
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pad(1);
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sh7305_pfc_control_t PTCR;
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sh7305_pfc_control_t PUCR;
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sh7305_pfc_control_t PVCR;
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pad(6);
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sh7305_pfc_control_t PPCR;
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/* PSEM*: Multiplexing pin settings. These are highly MPU-dependent and
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the assignment is basically unknown.
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HIZCR*: High-impedance settings for pins' I/O buffers. */
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uint16_t PSELA;
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uint16_t PSELB;
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uint16_t PSELC;
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uint16_t PSELD;
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uint16_t PSELE;
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uint16_t HIZCRA;
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uint16_t HIZCRB;
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uint16_t HIZCRC;
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uint16_t PSELF;
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sh7305_pfc_data_t PTDR;
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pad(1);
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sh7305_pfc_data_t PUDR;
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pad(1);
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sh7305_pfc_data_t PVDR;
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pad(5);
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sh7305_pfc_data_t PPDR;
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pad(0x15);
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/* Module function selection registers.
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WARNING: These are the SH7724 bits, not necessarily the SH7305! */
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word_union(MSELCRA,
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uint16_t :16;
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);
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word_union(MSELCRB,
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uint16_t XTAL_USB :2;
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uint16_t :6;
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uint16_t SCIF2_PORT :1;
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uint16_t :1;
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uint16_t SCIF3_PORT :1;
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uint16_t :3;
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uint16_t LDC_VSYNC_DIR :1;
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uint16_t :1;
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);
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// TODO: Doc
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uint16_t DRVCRD, DRVCRA, DRVCRB, DRVCRC;
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pad(4);
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/* Pull-up control registers. Not sure what these are since that's
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normally handled in the modes for P*CR? */
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uint8_t PULCRA, PULCRB, PULCRC, PULCRD, PULCRE, PULCRF, PULCRG,
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PULCRH, PULCRJ, PULCRK, PULCRL, PULCRM, PULCRN, PULCRQ,
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PULCRR, PULCRS;
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pad(0x20);
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uint8_t PULCRT;
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uint8_t PULCRU;
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uint8_t PULCRV;
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uint8_t PULCRBSC;
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pad(1);
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uint8_t PULCRTRST;
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uint8_t PULCRP;
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pad(1);
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uint16_t PSELG;
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pad(12);
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uint16_t PSELH;
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} sh7305_pfc_t;
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#define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100))
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#ifdef __cplusplus
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}
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#endif
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