WIP - added SH3 OC functions and parameters
This commit is contained in:
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12c40b2980
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2fe00a712d
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@ -1,4 +1,4 @@
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/---
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//---
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// gint:mpu:wdt - Watchdog Timer
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//---
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@ -14,10 +14,15 @@
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#include <gint/hardware.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/wdt.h>
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define CPGSH3 SH7705_CPG
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#define BSCSH3 SH7705_BSC
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#define WDTSH3 SH7705_WDT
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//---
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// Low-level clock speed access
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//---
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@ -25,67 +30,111 @@
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#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(!isSH4())
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return;
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s->FLLFRQ = CPG.FLLFRQ.lword;
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s->FRQCR = CPG.FRQCR.lword;
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s->CS0BCR = BSC.CS0BCR.lword;
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s->CS0WCR = BSC.CS0WCR.lword;
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s->CS2BCR = BSC.CS2BCR.lword;
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s->CS2WCR = BSC.CS2WCR.lword;
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s->CS3BCR = BSC.CS3BCR.lword;
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s->CS3WCR = BSC.CS3WCR.lword;
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s->CS5aBCR = BSC.CS5ABCR.lword;
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s->CS5aWCR = BSC.CS5AWCR.lword;
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}
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void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(!isSH4())
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return;
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BSC.CS0WCR.WR = 11; /* 18 cycles */
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CPG.FLLFRQ.lword = s->FLLFRQ;
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CPG.FRQCR.lword = s->FRQCR;
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CPG.FRQCR.KICK = 1;
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while(CPG.LSTATS != 0) {}
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BSC.CS0BCR.lword = s->CS0BCR;
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BSC.CS0WCR.lword = s->CS0WCR;
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BSC.CS2BCR.lword = s->CS2BCR;
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BSC.CS2WCR.lword = s->CS2WCR;
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BSC.CS3BCR.lword = s->CS3BCR;
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BSC.CS3WCR.lword = s->CS3WCR;
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if(BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = s->CS5aBCR;
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BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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//---
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// Predefined clock speeds
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//---
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#define PLL_32x 0b011111
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#define PLL_26x 0b011001
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#define PLL_16x 0b001111
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#define DIV_2 0
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#define DIV_4 1
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#define DIV_8 2
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#define DIV_16 3
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#define DIV_32 4
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// for SH4 based calculators
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#define SH4_PLL_32x 0b011111
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#define SH4_PLL_26x 0b011001
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#define SH4_PLL_16x 0b001111
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#define SH4_DIV_2 0
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#define SH4_DIV_4 1
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#define SH4_DIV_8 2
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#define SH4_DIV_16 3
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#define SH4_DIV_32 4
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// for SH3 based calculators
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#define SH3_PLL_1x 0 //0b0000 // x1
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#define SH3_PLL_2x 1 //0b0001 // x2
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#define SH3_PLL_3x 2 //0b0010 // x3
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#define SH3_PLL_4x 3 //0b0011 // x4
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#define SH3_DIV_1 0 //0b0000 // 1/1
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#define SH3_DIV_2 1 //0b0001 // 1/2
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#define SH3_DIV_3 2 //0b0010 // 1/3
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#define SH3_DIV_4 3 //0b0011 // 1/4
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(isSH3())
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{
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s->FLLFRQ = 0xFFFFFFF; // not used for SH3 MPUs
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s->FRQCR = CPGSH3.FRQCR.word;
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s->CS0BCR = BSCSH3.CS0BCR.lword;
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s->CS0WCR = BSCSH3.CS0WCR.lword;
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s->CS2BCR = BSCSH3.CS2BCR.lword;
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s->CS2WCR = BSCSH3.CS2WCR.lword;
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s->CS3BCR = BSCSH3.CS3BCR.lword;
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s->CS3WCR = BSCSH3.CS3WCR.lword;
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s->CS5aBCR = BSCSH3.CS5ABCR.lword;
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s->CS5aWCR = BSCSH3.CS5AWCR.lword;
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}
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else if(isSH4())
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{
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s->FLLFRQ = CPG.FLLFRQ.lword;
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s->FRQCR = CPG.FRQCR.lword;
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s->CS0BCR = BSC.CS0BCR.lword;
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s->CS0WCR = BSC.CS0WCR.lword;
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s->CS2BCR = BSC.CS2BCR.lword;
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s->CS2WCR = BSC.CS2WCR.lword;
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s->CS3BCR = BSC.CS3BCR.lword;
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s->CS3WCR = BSC.CS3WCR.lword;
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s->CS5aBCR = BSC.CS5ABCR.lword;
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s->CS5aWCR = BSC.CS5AWCR.lword;
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}
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else return;
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}
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void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(isSH3())
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{
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WDTSH3.WTCNT.WRITE = 0;
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WDTSH3.WTCNT.WRITE = 0x65;
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CPGSH3.FRQCR.word = 0x1000 | s->FRQCR;
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BSCSH3.CS0BCR.lword = s->CS0BCR;
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BSCSH3.CS0WCR.lword = s->CS0WCR;
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BSCSH3.CS2BCR.lword = s->CS2BCR;
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BSCSH3.CS2WCR.lword = s->CS2WCR;
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BSCSH3.CS3BCR.lword = s->CS3BCR;
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BSCSH3.CS3WCR.lword = s->CS3WCR;
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BSCSH3.CS5ABCR.lword = s->CS5aBCR;
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BSCSH3.CS5AWCR.lword = s->CS5aWCR;
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}
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else if(isSH4())
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{
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BSC.CS0WCR.WR = 11; /* 18 cycles */
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CPG.FLLFRQ.lword = s->FLLFRQ;
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CPG.FRQCR.lword = s->FRQCR;
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CPG.FRQCR.KICK = 1;
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while(CPG.LSTATS != 0) {}
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BSC.CS0BCR.lword = s->CS0BCR;
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BSC.CS0WCR.lword = s->CS0WCR;
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BSC.CS2BCR.lword = s->CS2BCR;
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BSC.CS2WCR.lword = s->CS2WCR;
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BSC.CS3BCR.lword = s->CS3BCR;
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BSC.CS3WCR.lword = s->CS3WCR;
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if(BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = s->CS5aBCR;
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BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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else return;
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}
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/*settings for the fxcg50 / G90+E*/
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static struct cpg_overclock_setting settings_cg50[5] = {
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static struct cpg_overclock_setting settings_fxcg50[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F011112,
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@ -99,7 +148,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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@ -110,7 +159,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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@ -121,7 +170,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV_16,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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@ -132,7 +181,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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@ -144,7 +193,7 @@ static struct cpg_overclock_setting settings_cg50[5] = {
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};
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/*settings for the prizm fxcg10/20*/
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static struct cpg_overclock_setting settings_cg20[5] = {
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static struct cpg_overclock_setting settings_prizm[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F102203,
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@ -158,7 +207,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_8<<20)+(DIV_16<<12)+(DIV_16<<8)+DIV_32,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_16<<12)+(SH4_DIV_16<<8)+SH4_DIV_32,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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@ -169,7 +218,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_32,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_32,
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.CS0BCR = 0x24900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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@ -180,7 +229,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_32,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_32,
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.CS0BCR = 0x44900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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@ -191,7 +240,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_16,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
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.CS0BCR = 0x34900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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@ -202,8 +251,68 @@ static struct cpg_overclock_setting settings_cg20[5] = {
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.CS5aWCR = 0x00010240 },
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};
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/*settings for the fx9860G SH3 based*/
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static struct cpg_overclock_setting settings_fx9860g_sh3[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = 0x1001,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_2x<<8)+(SH3_DIV_1<<4)+SH3_DIV_2,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_3x<<8)+(SH3_DIV_1<<4)+SH3_DIV_3,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000000C0,
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.CS2WCR = 0x000100C0,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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};
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/*settings for the fx9860GII*/
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static struct cpg_overclock_setting settings_fx9860gII[5] = {
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static struct cpg_overclock_setting settings_fx9860g_sh4[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = 0x0F202203,
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@ -217,7 +326,7 @@ static struct cpg_overclock_setting settings_fx9860gII[5] = {
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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@ -228,7 +337,7 @@ static struct cpg_overclock_setting settings_fx9860gII[5] = {
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = PLL_16x<<24)+(DIV_8<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -239,7 +348,7 @@ static struct cpg_overclock_setting settings_fx9860gII[5] = {
|
|||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -250,7 +359,7 @@ static struct cpg_overclock_setting settings_fx9860gII[5] = {
|
|||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -262,7 +371,7 @@ static struct cpg_overclock_setting settings_fx9860gII[5] = {
|
|||
};
|
||||
|
||||
/*settings for the fx9860GII-2 / G35+EII*/
|
||||
static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
||||
static struct cpg_overclock_setting settings_g35pe2[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = 0x0F202203,
|
||||
|
|
@ -276,7 +385,7 @@ static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
|||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -287,7 +396,7 @@ static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
|||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_16x<<24)+(DIV_8<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -298,7 +407,7 @@ static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
|||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -309,7 +418,7 @@ static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
|||
.CS5aWCR = 0x00031340 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV16,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -323,13 +432,15 @@ static struct cpg_overclock_setting settings_fx9860gII2[5] = {
|
|||
static struct cpg_overclock_setting *get_settings(void)
|
||||
{
|
||||
if(gint[HWCALC] == HWCALC_FXCG50)
|
||||
return settings_cg50;
|
||||
return settings_fxcg50;
|
||||
if(gint[HWCALC] == HWCALC_PRIZM)
|
||||
return settings_cg20;
|
||||
return settings_prizm;
|
||||
if(gint[HWCALC] == HWCALC_G35PE2)
|
||||
return settings_fx9860gII2;
|
||||
return settings_g35pe2;
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH4)
|
||||
return settings_fx9860gII;
|
||||
return settings_fx9860g_sh4;
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH3)
|
||||
return settings_fx9860g_sh3;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue