tmu: export definitions, clean stop, expose address
This commit introduces three timer driver changes: * Export the definitions of the timer structures to a detailed header at <gint/mpu/tmu.h>, and re-use them in the driver. This integration is still limited as the driver keeps its own address definitions and event codes. * Clean the timer stop routine that is used in the interrupt handler. Up until now the interrupt handler would only stop TSTR, which is not enough to cleanly leave the timer (need TCOR=TCNT=-1) and is not even sound with respect to gint's semantics as UNIE stays enabled so the timer is not made available again. The interrupt handler now calls into C code when the timer stop condition is met (callback returns non-zero) to keep this clean. This unsurprisingly solves problems that occurred in certain situations when a timer was used repeatedly. * Expose timer addresses using a timer_address() function, compensating for the lack of address definitions in <gint/mpu/tmu.h>. This interface is likely to evolve in the future to better integrate the address in the MPU headers and move them out of the driver.
This commit is contained in:
lephe
parent
7e09e37938
commit
31ade70c42
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@ -0,0 +1,89 @@
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//---
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// gint:intc:tmu - Timer Unit
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//
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// The definitions in this file cover both the Timer Unit and the Extra
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// Timers. The structures are related but not identical; the behaviour is
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// subtly different.
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//---
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#ifndef GINT_MPU_TMU
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#define GINT_MPU_TMU
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#include <gint/defs/types.h>
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//---
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// Common structures
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//---
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/* tmu_t - a single timer from a standard timer unit */
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typedef volatile struct
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{
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uint32_t TCOR; /* Constant register */
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uint32_t TCNT; /* Counter register, counts down */
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word_union(TCR,
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uint16_t :7;
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uint16_t UNF :1; /* Underflow flag */
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uint16_t :2;
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uint16_t UNIE :1; /* Underflow interrupt enable */
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uint16_t CKEG :2; /* Input clock edge */
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uint16_t TPSC :3; /* Timer prescaler (input clock) */
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);
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} GPACKED(4) tmu_t;
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/* etmu_t - extra timers on SH7337, SH7355 and SH7305 */
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typedef volatile struct
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{
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uint8_t TSTR; /* Only bit 0 is used */
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pad(3);
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uint32_t TCOR; /* Constant register */
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uint32_t TCNT; /* Counter register */
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byte_union(TCR,
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uint8_t :6;
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uint8_t UNF :1; /* Underflow flag */
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uint8_t UNIE :1; /* Underflow interrupt enable */
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);
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} GPACKED(4) etmu_t;
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//---
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// SH7705 Timer Unit. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 12: "Timer Unit (TMU)"
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//---
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typedef volatile struct
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{
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pad(2);
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uint8_t TSTR; /* Timer Start Register */
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pad(1);
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tmu_t TMU[3];
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uint32_t TCPR2; /* Timer Input Capture Register 2 */
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} GPACKED(4) sh7705_tmu_t;
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#define SH7705_TMU (*((sh7705_tmu_t *)0xfffffe90))
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//---
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// SH7305 Timer Unit. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 20: "Timer Unit (TMU)"
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//---
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typedef volatile struct
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{
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uint8_t TSTR; /* Timer Start Register */
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pad(3);
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tmu_t TMU[3];
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} GPACKED(4) sh7305_tmu_t;
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#define SH7305_TMU (*((sh7305_tmu_t *)0xa4490004))
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#endif /* GINT_MPU_TMU */
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@ -6,6 +6,7 @@
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#define GINT_TIMER
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#include <gint/defs/types.h>
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#include <gint/mpu/tmu.h>
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#include <gint/hardware.h>
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/* Timer identifiers
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@ -151,4 +152,16 @@ void timer_stop(int timer);
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int * and you must declare the variable as volatile int. */
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int timer_timeout(volatile void *arg);
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//---
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// Low-level functions
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//---
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/* timer_address() - get the address of a timer structure
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Returns a tmu_t if the id is 0, 1 or 2 and an etmu_t otherwise. The address
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will be NULL if the requested timer does not exist.
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@timer Requested timer
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@TSTR If the requested timer is a TMU, set to the TSTR address */
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void *timer_address(int timer, volatile uint8_t **TSTR);
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#endif /* GINT_TIMER */
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137
src/tmu/inth.s
137
src/tmu/inth.s
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@ -12,9 +12,9 @@
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.global _inth_tmu_storage
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/* Gates for the extra timers (informally called ETMU) */
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.global _inth_tmu_extra2
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.global _inth_tmu_extra_help
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.global _inth_tmu_extra_others
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.global _inth_etmu2
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.global _inth_etmu_help
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.global _inth_etmux
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.section .gint.blocks, "ax"
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.align 4
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@ -39,11 +39,12 @@
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/* FIRST GATE - TMU0 entry, clear underflow flag and call back */
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_inth_tmu_0:
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mova .storage0, r0
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mov #-2, r1
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mov #0, r1
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/*** This is the first shared section ***/
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.clearflag:
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sts.l pr, @-r15
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mov.l r1, @-r15
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/* Load the TCR address and clear the interrupt flag */
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@ -54,22 +55,21 @@ _inth_tmu_0:
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mov.w r2, @r1
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/* Invoke the callback function and pass the argument */
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sts.l pr, @-r15
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mov.l @r0, r1
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jsr @r1
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mov.l @(4, r0), r4
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lds.l @r15+, pr
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/* Prepare stopping the timer and jump to second section */
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mov.l .tstr, r5
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mov.l @r15+, r4
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mov.l .timer_stop, r1
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bra .stoptimer
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mov.l @r15+, r1
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nop
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/* SECOND GATE - TMU1 entry and stop timer */
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_inth_tmu_1:
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mova .storage1, r0
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bra .clearflag
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mov #-3, r1
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mov #1, r1
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/*** This is the second shared section ***/
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@ -77,11 +77,11 @@ _inth_tmu_1:
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/* Stop the timer if the return value is not zero */
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tst r0, r0
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bt .end
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mov.b @r5, r2
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and r1, r2
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mov.b r2, @r5
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jsr @r1
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nop
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.end:
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lds.l @r15+, pr
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rte
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nop
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@ -91,7 +91,7 @@ _inth_tmu_1:
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_inth_tmu_2:
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mova .storage2, r0
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bra .clearflag
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mov #-5, r1
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mov #2, r1
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.zero 14
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@ -103,8 +103,10 @@ _inth_tmu_2:
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/* FOURTH GATE - Storage for TMU1, TMU2 and other values */
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_inth_tmu_storage:
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.mask: .long 0x0000feff
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.tstr: .long 0xa4490004 /* TSTR: Overridden at startup on SH3 */
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.mask:
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.long 0x0000feff
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.timer_stop:
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.long _timer_stop /* gint's function from <gint/timer.h> */
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.storage1:
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.long 0 /* Callback: Configured dynamically */
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@ -139,87 +141,72 @@ _inth_tmu_storage:
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can think of is hardcoding the relative displacements, and one would need to
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use the unnatural and unmaintainable @(disp, pc) addressing modes. */
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/* FIRST GATE - ETMU2 entry, clear flag and prepare callback */
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_inth_tmu_extra2:
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/* Warning: the size of the following instruction (2 bytes) is
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hardcoded in another interrupt handler, _inth_tmu_extra_others */
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mova .storage_extra_1, r0
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/* FIRST GATE - ETMU2 entry, invoke callback and prepare clear flag */
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_inth_etmu2:
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/* Warning: the size of the following section (4 bytes) is hardcoded in
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the jump in _inth_etmux */
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mova .storage_etmu2, r0
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mov #5, r1
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.extra_callback:
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mov.l r8, @-r15
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mov r0, r8
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stc.l gbr, @-r15
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sts.l pr, @-r15
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mov.l r1, @-r15
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/* Invoke the callback function */
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sts.l pr, @-r15
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mov.l @r8, r1
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mov.l @r0, r1
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jsr @r1
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mov.l @(4, r8), r4
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mov.l @(4, r0), r4
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bra .extra_clearflag
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lds.l @r15+, pr
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.storage_extra_1:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0 /* Structure address: Edited at startup */
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/* SECOND GATE - Helper entry, invoke callback and stop timer if requested */
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_inth_tmu_extra_help:
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.extra_clearflag:
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/* Load timer ID and forward the callback's return value */
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mov.l .timer_clear, r1
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mov.l @r15+, r4
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bra _inth_etmu_help
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mov r0, r5
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/* Load struture address */
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mov.l @(8, r8), r0
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ldc r0, gbr
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mov #12, r0
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nop
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.extra_loopclear:
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/* Aggressively clear the interrupt flag. The loop is required because
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clearing takes "some time". The system does it. Not doing it will
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cause the interrupt to be triggered again until the flag is cleared,
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which can be ~20 interrupts if the handler is fast! */
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and.b #0xfd, @(r0, gbr)
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tst.b #0x02, @(r0, gbr)
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bf .extra_loopclear
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.storage_etmu2:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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/* Check whether to stop the timer */
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tst r5, r5
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bt .extra_end
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/* SECOND GATE - Helper entry, invoke callback and stop timer if requested */
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_inth_etmu_help:
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.extra_stoptimer:
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mov.b @(0, gbr), r0
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and #0xfe, r0
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mov.b r0, @(0, gbr)
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/* Clear the flag and possibly stop the timer */
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jsr @r1
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nop
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.extra_end:
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ldc.l @r15+, gbr
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mov.l @r15+, r8
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lds.l @r15+, pr
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rte
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nop
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/* FOURTH GATE - All other ETMU entries, deferred to the previous ones */
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_inth_tmu_extra_others:
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/* Dynamically compute the target of the jump */
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stc vbr, r1
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mov.l 1f, r2
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add r2, r1
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.zero 18
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mova .storage_extra_others, r0
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jmp @r1
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.timer_clear:
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.long _timer_clear /* gint's function from src/tmu/tmu.c */
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/* THIRD GATE - All other ETMU entries, deferred to the previous ones */
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_inth_etmux:
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/* Dynamically compute the target of the jump */
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stc vbr, r3
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mov.l 1f, r2
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add r2, r3
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mova .storage_etmux, r0
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mov.l .id_etmux, r1
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jmp @r3
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nop
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nop
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/* Offset from VBR where extra timer 2 is located:
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- 0x600 to reach the interrupt handlers
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- 0x020 to jump over the entry gate
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- 0x840 to reach the handler of extra timer 2
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- 0x002 to skip its first instruction (the size is hardcoded) */
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1: .long 0xe62
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- 0x840 to reach the handler of ETMU2
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- 0x004 to skip its first instructions (the size is hardcoded) */
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1: .long 0xe64
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.zero 4
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.storage_extra_others:
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.storage_etmux:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0 /* Structure address: Edited at startup */
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.id_etmux:
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.long 0 /* Timer ID */
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@ -10,8 +10,7 @@ void sleep_us(int tid, int us_delay)
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{
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volatile int flag = 0;
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timer_setup(tid, timer_delay(tid, us_delay), 0, timer_timeout,
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(void *)&flag);
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timer_setup(tid, timer_delay(tid, us_delay), 0, timer_timeout, &flag);
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timer_start(tid);
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while(!flag) sleep();
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109
src/tmu/tmu.c
109
src/tmu/tmu.c
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@ -8,6 +8,7 @@
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#include <gint/clock.h>
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#include <gint/mpu/intc.h>
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#include <gint/mpu/tmu.h>
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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@ -16,46 +17,13 @@
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// Timer structures
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//---
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/* tmu_t - a single timer from a standard timer unit */
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typedef volatile struct
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{
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uint32_t TCOR; /* Constant register */
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uint32_t TCNT; /* Counter register, counts down */
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word_union(TCR,
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uint16_t :7;
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uint16_t UNF :1; /* Underflow flag */
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uint16_t :2;
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uint16_t UNIE :1; /* Underflow interrupt enable */
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uint16_t CKEG :2; /* Input clock edge */
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uint16_t TPSC :3; /* Timer prescaler (input clock) */
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);
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} GPACKED(4) tmu_t;
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/* tmu_extra_t - extra timers on sh7337, sh7355 and sh7305 */
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typedef volatile struct
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{
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uint8_t TSTR; /* Only bit 0 is used */
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pad(3);
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uint32_t TCOR; /* Constant register */
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uint32_t TCNT; /* Counter register */
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byte_union(TCR,
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uint8_t :6;
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uint8_t UNF :1; /* Underflow flag */
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uint8_t UNIE :1; /* Underflow interrupt enable */
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);
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} GPACKED(4) tmu_extra_t;
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/* inth_data_t - data storage inside interrupt handlers */
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typedef struct
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{
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int (*cb)(volatile void *arg); /* User-provided callback */
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volatile void *arg; /* Argument for [callback] */
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volatile void *structure; /* Either TCR or timer address */
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volatile void *TCR; /* TCR address for TMU */
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} GPACKED(4) inth_data_t;
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@ -119,7 +87,7 @@ int timer_setup(int tid, uint32_t delay, timer_input_t clock,
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/* Extra timers have a simpler structure */
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else
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{
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tmu_extra_t *t = timers[tid].tmu;
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etmu_t *t = timers[tid].tmu;
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if(t->TCR.UNIE) return -1;
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/* Clear the interrupt flag */
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@ -173,7 +141,7 @@ static void timer_control(int tid, int state)
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/* For standard timers, use the MPU's TSTR register */
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if(tid < 3) *TSTR = (*TSTR | (1 << tid)) ^ (state << tid);
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/* Extra timers all have their own TSTR register */
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else ((tmu_extra_t *)timers[tid].tmu)->TSTR = state ^ 1;
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else ((etmu_t *)timers[tid].tmu)->TSTR = state ^ 1;
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}
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/* timer_start() - start a configured timer */
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@ -186,7 +154,7 @@ void timer_start(int tid)
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void timer_reload(int tid, uint32_t delay)
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{
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if(tid < 3) ((tmu_t *)timers[tid].tmu)->TCOR = delay;
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else ((tmu_extra_t *)timers[tid].tmu)->TCOR = delay;
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else ((etmu_t *)timers[tid].tmu)->TCOR = delay;
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}
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/* timer_pause() - stop a running timer */
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@ -205,10 +173,14 @@ void timer_stop(int tid)
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{
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tmu_t *t = timers[tid].tmu;
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t->TCR.UNIE = 0;
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/* Clear TCOR and TCNT */
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t->TCOR = 0xffffffff;
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t->TCNT = 0xffffffff;
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}
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else
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{
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tmu_extra_t *t = timers[tid].tmu;
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etmu_t *t = timers[tid].tmu;
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t->TCR.UNIE = 0;
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/* Also clear TCOR and TCNT to avoid spurious interrupts */
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@ -232,7 +204,32 @@ int timer_timeout(volatile void *arg)
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{
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volatile int *x = arg;
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(*x)++;
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return 0;
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/* Always stop after firing once */
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return 1;
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}
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//---
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// Low-level functions
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//---
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/* timer_address() - get the address of a timer structure */
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void *timer_address(int timer, volatile uint8_t **TSTR_arg)
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{
|
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if((uint)timer < 2 && TSTR_arg) *TSTR_arg = TSTR;
|
||||
return (uint)timer < timer_count() ? timers[timer].tmu : NULL;
|
||||
}
|
||||
|
||||
/* timer_clear() - clear an ETMU flag and possibly stop the timer
|
||||
@timer Timer ID, must be an ETMU
|
||||
@stop Non-zero to stop the timer */
|
||||
void timer_clear(int timer, int stop)
|
||||
{
|
||||
etmu_t *t = timers[timer].tmu;
|
||||
do t->TCR.UNF = 0;
|
||||
while(t->TCR.UNF);
|
||||
|
||||
if(stop) timer_stop(timer);
|
||||
}
|
||||
|
||||
//---
|
||||
|
|
@ -246,10 +243,9 @@ extern void inth_tmu_2(void);
|
|||
extern void inth_tmu_storage(void);
|
||||
|
||||
/* Interrupt handlers provided by tmu/inth.s for extra timers */
|
||||
extern void inth_tmu_extra1(void);
|
||||
extern void inth_tmu_extra2(void);
|
||||
extern void inth_tmu_extra_help(void);
|
||||
extern void inth_tmu_extra_others(void);
|
||||
extern void inth_etmu2(void);
|
||||
extern void inth_etmu_help(void);
|
||||
extern void inth_etmux(void);
|
||||
|
||||
#ifdef FX9860G
|
||||
static void driver_sh3(void)
|
||||
|
|
@ -297,13 +293,13 @@ static void init(void)
|
|||
while(t->TCR.word);
|
||||
|
||||
/* Standard timers: TCR is provided to the interrupt handler */
|
||||
timers[i].data->structure = &t->TCR;
|
||||
timers[i].data->TCR = &t->TCR;
|
||||
}
|
||||
|
||||
/* Clear the extra timers */
|
||||
for(int i = 3; i < timer_count(); i++)
|
||||
{
|
||||
tmu_extra_t *t = timers[i].tmu;
|
||||
etmu_t *t = timers[i].tmu;
|
||||
|
||||
/* Extra timers seem to generate interrupts as long as TCNT=0,
|
||||
regardless of TSTR. I'm not entirely sure about this weird
|
||||
|
|
@ -329,17 +325,18 @@ static void init(void)
|
|||
|
||||
for(int i = 3; i < limit; i++)
|
||||
{
|
||||
void *handler = (i == 5)
|
||||
? inth_tmu_extra2
|
||||
: inth_tmu_extra_others;
|
||||
void *handler = (i == 5) ? inth_etmu2 : inth_etmux;
|
||||
void *h = gint_inthandler(timers[i].event, handler, 32);
|
||||
|
||||
timers[i].data = h + 20;
|
||||
timers[i].data->structure = timers[i].tmu;
|
||||
timers[i].data = (i == 5) ? (h + 24) : (h + 20);
|
||||
|
||||
if(i == 5) continue;
|
||||
uint32_t *data_id = (h + 28);
|
||||
*data_id = i;
|
||||
}
|
||||
|
||||
/* Also install the helper handler */
|
||||
gint_inthandler(0xc60, inth_tmu_extra_help, 32);
|
||||
gint_inthandler(0xc60, inth_etmu_help, 32);
|
||||
|
||||
/* Enable TMU0 at level 13, TMU1 at level 11, TMU2 at level 9 */
|
||||
gint_intlevel(0, 13);
|
||||
|
|
@ -374,7 +371,7 @@ static void init(void)
|
|||
|
||||
for(int i = 3; i < timer_count(); i++)
|
||||
{
|
||||
tmu_extra_t *t = timers[i].tmu;
|
||||
etmu_t *t = timers[i].tmu;
|
||||
int v = !(t->TCOR + 1)
|
||||
&& !(t->TCNT + 1)
|
||||
&& !(t->TSTR)
|
||||
|
|
@ -412,7 +409,7 @@ static const char *tmu_status(void)
|
|||
int j = 5;
|
||||
for(int i = 3; i < timer_count(); i++)
|
||||
{
|
||||
tmu_extra_t *t = timers[i].tmu;
|
||||
etmu_t *t = timers[i].tmu;
|
||||
int v1 = (!(t->TCOR + 1))
|
||||
| (!(t->TCNT + 1) << 1)
|
||||
| (!(t->TSTR) << 2);
|
||||
|
|
@ -435,7 +432,7 @@ static const char *tmu_status(void)
|
|||
typedef struct
|
||||
{
|
||||
tmu_t std[3];
|
||||
tmu_extra_t extra[6];
|
||||
etmu_t extra[6];
|
||||
uint8_t TSTR;
|
||||
|
||||
} GPACKED(4) ctx_t;
|
||||
|
|
@ -459,7 +456,7 @@ static void ctx_save(void *buf)
|
|||
|
||||
for(int i = 0; i < timer_count() - 3; i++)
|
||||
{
|
||||
tmu_extra_t *t = timers[i + 3].tmu;
|
||||
etmu_t *t = timers[i + 3].tmu;
|
||||
ctx->extra[i].TCOR = t->TCOR;
|
||||
ctx->extra[i].TCNT = t->TCNT;
|
||||
ctx->extra[i].TCR.byte = t->TCR.byte;
|
||||
|
|
@ -483,7 +480,7 @@ static void ctx_restore(void *buf)
|
|||
|
||||
for(int i = 0; i < timer_count() - 3; i++)
|
||||
{
|
||||
tmu_extra_t *t = timers[i + 3].tmu;
|
||||
etmu_t *t = timers[i + 3].tmu;
|
||||
|
||||
/* This thing is being unloaded while interrupts are disabled,
|
||||
so we don't have to heed for ctx->extra[i].TCNT = 0, which
|
||||
|
|
|
|||
Loading…
Reference in New Issue