Point 0 - resync with Lephe's gint@dev
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@ -12,6 +12,84 @@ extern "C" {
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 But State Controller. Refer to:
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// Renesas SH7705 Group Hardware Manual
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// Section 7: Bus State Controller (BSC)
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//---
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typedef volatile lword_union(sh7705_bsc_CSnBCR_t,
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uint32_t :2;
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uint32_t IWW :2;
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uint32_t :1;
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uint32_t IWRWD :2;
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uint32_t :1;
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uint32_t IWRWS :2;
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uint32_t :1;
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uint32_t IWRRD :2;
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uint32_t :1;
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uint32_t IWRRS :2;
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uint32_t :1;
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uint32_t TYPE :3;
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uint32_t :1;
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uint32_t BSZ :2;
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uint32_t :9;
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);
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typedef volatile lword_union(sh7705_bsc_CSnWCR_t,
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uint32_t :13;
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uint32_t WW :3;
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uint32_t :3;
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uint32_t SW :2;
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uint32_t WR :4;
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uint32_t WM :1;
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uint32_t :4;
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uint32_t HW :2;
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);
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typedef volatile struct
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{
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lword_union(CMNCR,
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uint32_t :24; /* reserved */
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uint32_t DMAIW : 2; /* Wait State*/
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uint32_t DMAIWA : 1; /* Method of Inserting Wait state bewteen cycles */
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uint32_t :1; /* reserved */
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uint32_t ENDIAN : 1; /* Endian Flag*/
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uint32_t :1; /* reserved */
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uint32_t HIZMEM : 1; /* High Z memory Control*/
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uint32_t HIZCNT : 1; /* High Z Control*/
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);
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sh7705_bsc_CSnBCR_t CS0BCR;
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sh7705_bsc_CSnBCR_t CS2BCR;
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sh7705_bsc_CSnBCR_t CS3BCR;
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sh7705_bsc_CSnBCR_t CS4BCR;
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sh7705_bsc_CSnBCR_t CS5ABCR;
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sh7705_bsc_CSnBCR_t CS5BBCR;
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sh7705_bsc_CSnBCR_t CS6ABCR;
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sh7705_bsc_CSnBCR_t CS6BBCR;
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sh7705_bsc_CSnWCR_t CS0WCR;
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sh7705_bsc_CSnWCR_t CS2WCR;
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sh7705_bsc_CSnWCR_t CS3WCR;
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sh7705_bsc_CSnWCR_t CS4WCR;
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sh7705_bsc_CSnWCR_t CS5AWCR;
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sh7705_bsc_CSnWCR_t CS5BWCR;
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sh7705_bsc_CSnWCR_t CS6AWCR;
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sh7705_bsc_CSnWCR_t CS6BWCR;
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/* TODO : there are several other registers not described yet
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as they are not used for overclocking the SH7705 processor.
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To be done later on when needed.*/
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} GPACKED(4) sh7705_bsc_t;
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#define SH7705_BSC (*(sh7705_bsc_t *)0xa4fd0000)
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//---
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// SH7305 But State Controller. Refer to:
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// Renesas SH7730 Group Hardware Manual
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@ -31,6 +31,12 @@ typedef volatile struct
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uint16_t :2;
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uint16_t PFC :2; /* Peripheral clock divider */
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);
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byte_union(UCLKCR,
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uint8_t USSCS :2; /* Source Clock Selection Bit*/
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uint8_t USBEN :1; /* USB On-Chip Oscillator Enable*/
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uint8_t :5; /* reserved */
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);
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} GPACKED(4) sh7705_cpg_t;
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@ -79,6 +79,199 @@ typedef volatile struct
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// TODO: Document the SH7305 Pin Function Controller
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//---
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typedef volatile word_union( sh7305_Port_Control_Register_t,
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uint16_t P7MD :2;
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uint16_t P6MD :2;
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uint16_t P5MD :2;
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uint16_t P4MD :2;
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uint16_t P3MD :2;
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uint16_t P2MD :2;
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uint16_t P1MD :2;
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uint16_t P0MD :2;
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);
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typedef volatile byte_union( sh7305_port_data_register_t,
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uint8_t P7DT :1;
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uint8_t P6DT :1;
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uint8_t P5DT :1;
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uint8_t P4DT :1;
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uint8_t P3DT :1;
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uint8_t P2DT :1;
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uint8_t P1DT :1;
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uint8_t P0DT :1;
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);
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typedef volatile word_union( sh7305_pin_select_register_t,
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uint16_t PS15 :1;
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uint16_t PS14 :1;
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uint16_t PS13 :1;
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uint16_t PS12 :1;
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uint16_t PS11 :1;
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uint16_t PS10 :1;
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uint16_t PS9 :1;
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uint16_t PS8 :1;
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uint16_t PS7 :1;
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uint16_t PS6 :1;
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uint16_t PS5 :1;
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uint16_t PS4 :1;
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uint16_t PS3 :1;
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uint16_t PS2 :1;
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uint16_t PS1 :1;
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uint16_t PS0 :1;
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);
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typedef volatile word_union( sh7305_IO_buffer_hiz_control_register_t,
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uint16_t HIZ15 :1;
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uint16_t HIZ14 :1;
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uint16_t HIZ13 :1;
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uint16_t HIZ12 :1;
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uint16_t HIZ11 :1;
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uint16_t HIZ10 :1;
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uint16_t HIZ9 :1;
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uint16_t HIZ8 :1;
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uint16_t HIZ7 :1;
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uint16_t HIZ6 :1;
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uint16_t HIZ5 :1;
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uint16_t HIZ4 :1;
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uint16_t HIZ3 :1;
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uint16_t HIZ2 :1;
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uint16_t HIZ1 :1;
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uint16_t HIZ0 :1;
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);
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typedef volatile word_union( sh7305_module_function_select_register_t,
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uint16_t MSEL15 :1;
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uint16_t MSEL14 :1;
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uint16_t MSEL13 :1;
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uint16_t MSEL12 :1;
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uint16_t MSEL11 :1;
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uint16_t MSEL10 :1;
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uint16_t MSEL9 :1;
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uint16_t MSEL8 :1;
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uint16_t MSEL7 :1;
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uint16_t MSEL6 :1;
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uint16_t MSEL5 :1;
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uint16_t MSEL4 :1;
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uint16_t MSEL3 :1;
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uint16_t MSEL2 :1;
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uint16_t MSEL1 :1;
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uint16_t MSEL0 :1;
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);
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typedef volatile word_union( sh7305_IO_buffer_drive_control_register_t,
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uint16_t DRV15 :1;
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uint16_t DRV14 :1;
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uint16_t DRV13 :1;
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uint16_t DRV12 :1;
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uint16_t DRV11 :1;
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uint16_t DRV10 :1;
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uint16_t DRV9 :1;
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uint16_t DRV8 :1;
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uint16_t DRV7 :1;
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uint16_t DRV6 :1;
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uint16_t DRV5 :1;
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uint16_t DRV4 :1;
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uint16_t DRV3 :1;
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uint16_t DRV2 :1;
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uint16_t DRV1 :1;
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uint16_t DRV0 :1;
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);
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typedef volatile struct
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{
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// List of all PORT CONTROL REGISTERS (PCRs)
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sh7305_Port_Control_Register_t PACR;
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sh7305_Port_Control_Register_t PBCR;
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sh7305_Port_Control_Register_t PCCR;
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sh7305_Port_Control_Register_t PDCR;
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sh7305_Port_Control_Register_t PECR;
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sh7305_Port_Control_Register_t PFCR;
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sh7305_Port_Control_Register_t PGCR;
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sh7305_Port_Control_Register_t PHCR;
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sh7305_Port_Control_Register_t PJCR;
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sh7305_Port_Control_Register_t PKCR;
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sh7305_Port_Control_Register_t PLCR;
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sh7305_Port_Control_Register_t PMCR;
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sh7305_Port_Control_Register_t PNCR;
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sh7305_Port_Control_Register_t PQCR;
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sh7305_Port_Control_Register_t PRCR;
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sh7305_Port_Control_Register_t PSCR;
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// List of all PORT DATA REGISTERS (PDRs)
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sh7305_port_data_register_t PADR;
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sh7305_port_data_register_t PBDR;
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sh7305_port_data_register_t PCDR;
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sh7305_port_data_register_t PDDR;
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sh7305_port_data_register_t PEDR;
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sh7305_port_data_register_t PFDR;
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sh7305_port_data_register_t PGDR;
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sh7305_port_data_register_t PHDR;
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sh7305_port_data_register_t PJDR;
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sh7305_port_data_register_t PKDR;
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sh7305_port_data_register_t PLDR;
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sh7305_port_data_register_t PMDR;
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sh7305_port_data_register_t PNDR;
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sh7305_port_data_register_t PQDR;
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sh7305_port_data_register_t PRDR;
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sh7305_port_data_register_t PSDR;
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sh7305_Port_Control_Register_t PTCR;
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sh7305_Port_Control_Register_t PUCR;
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sh7305_Port_Control_Register_t PVCR;
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//Missing ports ?
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//sh7305_Port_Control_Register_t PWCR;
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//sh7305_Port_Control_Register_t PXCR;
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//sh7305_Port_Control_Register_t PYCR;
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//sh7305_Port_Control_Register_t PZCR;
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pad( 0x08 );
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// List of all PIN SELECT REGISTERS (PSELs)
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sh7305_pin_select_register_t PSELA;
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sh7305_pin_select_register_t PSELB;
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sh7305_pin_select_register_t PSELC;
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sh7305_pin_select_register_t PSELD;
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sh7305_pin_select_register_t PSELE;
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// List of all IO BUFFER HI-Z CONTROL REGISTERS (HIZCRs)
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sh7305_IO_buffer_hiz_control_register_t HIZCRA;
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sh7305_IO_buffer_hiz_control_register_t HIZCRB;
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sh7305_IO_buffer_hiz_control_register_t HIZCRC;
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// the next one is not clearly listed, can be aither PSELF or HIZCRD so we skip it with pad
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//sh7305_pin_select_register_t PSELF;
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//sh7305_IO_buffer_hiz_control_register_t HIZCRD;
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pad( 0x02 );
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sh7305_port_data_register_t PTDR;
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sh7305_port_data_register_t PUDR;
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sh7305_port_data_register_t PVDR;
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//Missing ports ?
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//sh7305_port_data_register_t PWDR;
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//sh7305_port_data_register_t PXDR;
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//sh7305_port_data_register_t PYDR;
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//sh7305_port_data_register_t PZDR;
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pad( 0x08 );
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pad( 0x12 ); // jump from address 0xa405016e to 0xa4050180
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// List of all MODULE FUNCTION SELECT REGISTERS (MSELs)
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sh7305_module_function_select_register_t MSELCRA;
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sh7305_module_function_select_register_t MSELCRB;
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} sh7305_pfc_t;
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#define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100))
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,108 @@
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//---
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// gint:mpu:scif - Serial Communication Interface with FIFO (SCIF)
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//---
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#ifndef GINT_MPU_SCIF
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#define GINT_MPU_SCIF
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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typedef volatile struct
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{
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// Serial Mode
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word_union(SCSMR,
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uint16_t :8; //Reserved
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uint16_t CA :1; //Communication Mode.
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uint16_t CHR :1; //Character Length.
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uint16_t PE :1; //Parity Enable
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uint16_t OE :1; //Parity Mode
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uint16_t STOP :1; //Bit Stop Length
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uint16_t :1; //Reserved
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uint16_t CKS :2; //Clock Select
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);
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pad(0x2);
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// Serial Bit Rate
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uint8_t SCBRD; //set the bit rate of serial transmission/reception in relation to the operating clock of the baud rate generator
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pad(0x3);
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// Serial Control
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word_union(SCSCR,
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uint16_t :8; //Reserved
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uint16_t TIE :1; //Transmit Interrupt Enable
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uint16_t RIE :1; //Receive Interrupt Enable
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uint16_t TE :1; //Transmit Enable
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uint16_t RE :1; //Receive Mode
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uint16_t REIE :1; //Receive Error Interrupt Enable
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uint16_t :1; //Reserved
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uint16_t CKE :2; //Clock Enable
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);
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pad(0x2);
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// Serial Transmit data
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uint8_t SCFTD; // FIFO for serial transmit data
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pad(0x3);
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// Serial Status
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word_union(SCFSR,
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uint16_t PERC :4; //Number of Parity Errors
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uint16_t FERC :4; //Number of Framing Errors
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uint16_t ER :1; //Receive Error
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uint16_t TEND :1; //Transmit End
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uint16_t TDFE :1; //Transmit FIFO Data Empty
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uint16_t BRK :1; //Break Detection
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uint16_t FER :1; //Framing Error Indication
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uint16_t PER :1; //Parity Error Indication
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uint16_t RDF :1; //Receive FIFO Data Full
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uint16_t DR :1; //Received data Ready
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);
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pad(0x2);
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// Serial Receive data
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uint8_t SCFRD; // FIFO for serial received data
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pad(0x3);
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// Serial FIFO Control
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word_union(SCFCR,
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uint16_t :8; //Reserved
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uint16_t RTRG :2; //Receive FIFO Data Trigger
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uint16_t TTRG :2; //Transmit FIFO Data Trigger
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uint16_t :1; //Reserved
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uint16_t TFRST :1; //Transmit FIFO Data Register Reset
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uint16_t RFRST :1; //Receive FIFO Data Register Reset
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uint16_t LOOP :1; //Loopback Test
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);
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pad(0x2);
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// Serial FIFO Count
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word_union(SCFDR,
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uint16_t :3; //Reserved
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uint16_t TFDC :5; //Number of Data Bytes in Transmit FIFO
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uint16_t :3; //Reserved
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uint16_t RFDC :5; //Number of Data Bytes in Receive FIFO
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);
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pad(0x2);
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// Serial Line Status
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word_union(SCLSR,
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uint16_t :15; //Reserved
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uint16_t ORER :1; //Overrun Error
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);
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pad(0x2);
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} GPACKED(4) sh7305_scif_t;
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#define SH7305_SCIF (*((sh7305_scif_t *)0x0xa4410000))
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_SCIF */
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@ -0,0 +1,56 @@
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/---
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// gint:mpu:wdt - Watchdog Timer
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//---
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#ifndef GINT_MPU_WDT
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#define GINT_MPU_WDT
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 WatchDog Timer. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 10: "WatchDog Timer (WDT)"
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//---
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/* sh7705_wdt_t - Watch Dog Timer */
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typedef volatile struct
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{
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/* WDT registers are unique in access size; reads are performed with 8-bit
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accesses, but writes are performed with 16-bit accesses. */
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union {
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uint8_t READ;
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uint16_t WRITE;
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} WTCNT;
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union {
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byte_union(READ,
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uint8_t TME :1; /* ... description of TME */
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uint8_t WTIT :1; /* ... description of WT/IT */
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uint8_t RSTS :1; /* ... description of RSTS */
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uint8_t WOVF :1; /* ... description of WOVF */
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uint8_t IOVF :1; /* ... description of IOVF */
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uint8_t CKS :3; /* ... description of CKS */
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);
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uint16_t WRITE;
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} WTCSR;
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|
||||
} sh7705_wdt_t;
|
||||
|
||||
|
||||
#define SH7705_WDT (*((sh7705_wdt_t *)0xFFFFFF84))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GINT_MPU_WDT */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
//---
|
||||
// gint:serial - Serial operation
|
||||
//---
|
||||
|
||||
#ifndef GINT_SERIAL
|
||||
#define GINT_SERIAL
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <gint/mpu/scif.h>
|
||||
#include <gint/mpu/pfc.h>
|
||||
#include <gint/hardware.h>
|
||||
#include <gint/defs/types.h>
|
||||
#include <gint/defs/call.h>
|
||||
|
||||
|
||||
// Prototypes of functions expected to appear in the serial module
|
||||
// aims at reproducing the OS syscalls
|
||||
|
||||
int gint_serial_read_one_byte(unsigned char *dest);
|
||||
|
||||
int gint_serial_write_one_byte(unsigned char byte);
|
||||
|
||||
int gint_serial_write_bytes(unsigned char *src, int size);
|
||||
|
||||
int gint_serial_clear_receive_buffer(void);
|
||||
|
||||
int gint_serial_clear_transmit_buffer(void);
|
||||
|
||||
int gint_serial_open(unsigned char *conf);
|
||||
|
||||
int gint_serial_close(int mode);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GINT_SERIAL */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
//---
|
||||
// gint:serial - Serial operation
|
||||
//---
|
||||
|
||||
#include <gint/serial.h>
|
||||
|
||||
#define SCIF SH7305_SCIF
|
||||
#define PFC SH7305_PFC
|
||||
|
||||
|
||||
int gint_serial_read_one_byte(unsigned char *dest)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_write_one_byte(unsigned char byte)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_write_bytes(unsigned char *src, int size)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_clear_receive_buffer(void)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_clear_transmit_buffer(void)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_open(unsigned char *conf)
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
int gint_serial_close(int mode)
|
||||
{
|
||||
|
||||
};
|
||||
Loading…
Reference in New Issue