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ubc: panic when trying to break in code using register bank 1

This commit is contained in:
redoste 2023-06-04 17:57:49 +02:00
parent 0b7d8d6800
commit 6efcfa6018
Signed by: redoste
SSH Key Fingerprint: SHA256:Y1z/cbVN8OVoFPXzVgklSqoZnyQQ/PQM8YwhMtxMk90
2 changed files with 24 additions and 0 deletions
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2
src/kernel/exch.c
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@ -78,6 +78,7 @@ GNORETURN static void gint_default_panic(GUNUSED uint32_t code)
if(code == 0x1040) name = "Add-in too large";
if(code == 0x1060) name = "Memory init failed";
if(code == 0x1080) name = "Stack overflow";
if(code == 0x10a0) name = "UBC in bank 1 code";
if(name[0]) dtext(1, 9, name);
else dprint(1, 9, "%03x", code);
@ -118,6 +119,7 @@ GNORETURN static void gint_default_panic(GUNUSED uint32_t code)
if(code == 0x1040) name = "Add-in not fully mapped (too large)";
if(code == 0x1060) name = "Memory initialization failed (heap)";
if(code == 0x1080) name = "Stack overflow during world switch";
if(code == 0x10a0) name = "UBC break in register bank 1 code";
dprint(6, 25, "%03x %s", code, name);

22
src/ubc/ubc.S
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@ -14,6 +14,12 @@ _ubc_getDBR:
.global _ubc_dbh
_ubc_dbh:
/* We don't support breaking in a context where register bank 1 is used */
stc ssr, r0
mov.l .sr_rb1_mask, r1
tst r0, r1
bf .dbh_panic
/* We backup registers in the correct order to build gdb_cpu_state_t */
stc.l ssr, @-r15
sts.l macl, @-r15
@ -92,9 +98,25 @@ _ubc_dbh:
rte
nop
.dbh_panic:
stc sr, r1
mov.l .sr_mask, r0
and r0, r1
ldc r1, sr
mov.l .panic_code, r4
mov.l .panic, r0
mov.l @r0, r0
jmp @r0
nop
.align 4
.handler: .long _ubc_debug_handler
.ubc_dbh_lock: .long _ubc_dbh_lock
.panic_code: .long 0x10a0
.panic: .long _gint_exc_panic
.sr_rb1_mask: .long (1 << 29)
.sr_mask: .long ~0x300000f0 /* IMASK = 0 : mask no interrupts
BL = 0 : do not block interrupts
RB = 0 : use register BANK0