From 9b7951c3a2c5be3309a23e990af2f14b859bd633 Mon Sep 17 00:00:00 2001
From: Slyvtt <pillot.sylvain@gmail.com>
Date: Tue, 6 Dec 2022 18:48:44 +0100
Subject: [PATCH] Clean but still some bugs with SH3

---
 src/cpg/cpg.c       | 12 +-----------
 src/cpg/overclock.c |  4 ++--
 2 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/src/cpg/cpg.c b/src/cpg/cpg.c
index 4ecd7c8..a90033c 100644
--- a/src/cpg/cpg.c
+++ b/src/cpg/cpg.c
@@ -26,10 +26,7 @@ const clock_frequency_t *clock_freq(void)
 //	SH7705 Clock signals
 //---
 
-//#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
-//#define CPGSH3 SH7705_CPG
-
-void sh7705_probe(void)
+static void sh7705_probe(void)
 {
 	/* According to Sentaro21 in the sources of Ftune 1.0.1, the clock mode
 	   is thought to be 5, which means that:
@@ -69,15 +66,11 @@ void sh7705_probe(void)
 	freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
 }
 
-//#undef CPG
-//#endif /* FX9860G and platform-agnostic */
 
 //---
 //	SH7305 clock signals
 //---
 
-//#define CPGSH4 SH7305_CPG
-
 static void sh7305_probe(void)
 {
 	/* The meaning of the PLL setting on SH7305 differs from the
@@ -113,9 +106,6 @@ static void sh7305_probe(void)
 	freq.Pphi_f   = base >> (divp + 1);
 }
 
-//#undef CPG
-
-
 //---
 // Initialization
 //---
diff --git a/src/cpg/overclock.c b/src/cpg/overclock.c
index a5f74f7..2537f8a 100644
--- a/src/cpg/overclock.c
+++ b/src/cpg/overclock.c
@@ -99,8 +99,8 @@ void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
     if(isSH3())
     {
       SH7705_WDT.WTCNT.WRITE = 0;
-      SH7705_WDT.WTCNT.WRITE = 0x65;
-      SH7705_CPG.FRQCR.word = 0x1000 | (uint16_t) s->FRQCR;
+      SH7705_WDT.WTCSR.WRITE = 0x65;
+      SH7705_CPG.FRQCR.word = (uint16_t) (0x1000 | ((uint16_t) s->FRQCR));
       SH7705_BSC.CS0BCR.lword = s->CS0BCR;
       SH7705_BSC.CS0WCR.lword = s->CS0WCR;
       SH7705_BSC.CS2BCR.lword = s->CS2BCR;