From 9ba216d1de6f218abd8f44bbb2ad48a11c2330a3 Mon Sep 17 00:00:00 2001
From: Slyvtt <pillot.sylvain@gmail.com>
Date: Tue, 29 Nov 2022 21:13:05 +0100
Subject: [PATCH] some cleaning in pfc.h

---
 include/gint/mpu/pfc.h | 13 +------------
 include/gint/serial.h  |  2 ++
 src/scif/scif.c        | 35 -----------------------------------
 3 files changed, 3 insertions(+), 47 deletions(-)

diff --git a/include/gint/mpu/pfc.h b/include/gint/mpu/pfc.h
index 2bb94ba..23a362d 100644
--- a/include/gint/mpu/pfc.h
+++ b/include/gint/mpu/pfc.h
@@ -248,6 +248,7 @@ typedef volatile struct
 	sh7305_port_data_register_t PUDR;
 	sh7305_port_data_register_t PVDR;
 
+	//Missing ports ? 
 	//sh7305_port_data_register_t PWDR;
 	//sh7305_port_data_register_t PXDR;
 	//sh7305_port_data_register_t PYDR;
@@ -262,19 +263,7 @@ typedef volatile struct
 	sh7305_module_function_select_register_t MSELCRA;
 	sh7305_module_function_select_register_t MSELCRB;
 
-/*	
-	// PULL-UP CONTROL REGISTER (PULCR)
-	word_union( PULCR,
-		uint16_t PUL15 :1;
-		uint16_t reserved : 15;
-	);
 
-	// List of all IO BUFFER DRIVE CONTROL REGISTERS (DRVCRs)
-	sh7305_IO_buffer_drive_control_register_t DRVCRA;
-	sh7305_IO_buffer_drive_control_register_t DRVCRB;
-	sh7305_IO_buffer_drive_control_register_t DRVCRC;
-
-*/
 } sh7305_pfc_t;
 
 #define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100))
diff --git a/include/gint/serial.h b/include/gint/serial.h
index e7d7074..3b9c1e3 100644
--- a/include/gint/serial.h
+++ b/include/gint/serial.h
@@ -15,6 +15,8 @@ extern "C" {
 #include <gint/defs/call.h>
 
 
+// Prototypes of functions expected to appear in the serial module
+// aims at reproducing the OS syscalls
 
 int gint_serial_read_one_byte(unsigned char *dest);
 
diff --git a/src/scif/scif.c b/src/scif/scif.c
index 171645e..93396c2 100644
--- a/src/scif/scif.c
+++ b/src/scif/scif.c
@@ -34,41 +34,6 @@ int gint_serial_clear_transmit_buffer(void)
 
 int gint_serial_open(unsigned char *conf)
 {
-    SCIF.SCSCR.TE=0b0;
-    SCIF.SCSCR.RE=0b0;
-    SCIF.SCSCR.TIE=0b0;
-    SCIF.SCSCR.RIE=0b0;
-
-    SCIF.SCFCR.TFRST=0b1;
-    SCIF.SCFCR.RFRST=0b1;
-
-    SCIF.SCLCR.ORER=0b0;
-    SCIF.SCFSR.ER=0b0;
-    SCIF.SCFSR.DR=0b0;
-    SCIF.SCFSR.BRK=0b0;
-
-    SCIF.SCSCR.CKE=0b01;    //set to internal clock
-
-    SCIF.SCSMR.CA = 0b1; // clock synchronous mode
-    SCIF.SCSMR.CHR = 0b0; // 8bits length for data
-    SCIF.SCSMR.PE = 0b0; // Parity bit not set
-    SCIF.SCSMR.OE = 0b0; // just cleared, no effect as no parity is set
-    SCIF.SCSMR.STOP = 0b0; // not effect in synchronous mode
-    SCIF.SCSMR.CKS = 0b00; // 00=Pphi, 01=Pphi/4, 10=Pphi/16, 11=Pphi/64
-
-    SCIF.SCFCR.RTRG = 0b11;
-    SCIF.SCFCR.TTRG = 0b11;
-    SCIF.SCFCR.RFRST = 0b0;
-    SCIF.SCFCR.TFRST = 0b0;
-
-    //PFC setting for external pins used
-    //SCK, TXD, RXD
-
-    SCIF.SCSCR.TE=0b1;
-    SCIF.SCSCR.RE=0b1;
-    SCIF.SCSCR.TIE=0b1;
-    SCIF.SCSCR.RIE=0b1;
-    SCIF.SCSCR.REIE=0b1;
     
 };