usb: replace struct transfer with a more generic async. I/O op structure (WIP)
This lays the ground for both generalization to reading and sharing that logic with the serial driver.
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@ -0,0 +1,140 @@
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//---
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// gint:usb:asyncio - Asynchronous I/O common definitions
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//---
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#ifndef GINT_USB_ASYNCIO
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#define GINT_USB_ASYNCIO
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#include <gint/defs/types.h>
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#include <gint/defs/call.h>
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/* Data tracking the progress of a multi-part multi-round async I/O operation.
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* Multi-part refers to writes being constructed over several calls to
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write(2) followed by a "commit" with sync(2) (for async file descriptors;
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synchronous file descriptors are committed at every write).
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* Multi-round refers to the operation interacting multiple times with
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hardware in order to communicate the complete data.
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The process of performing such an I/O operation, as tracked by this
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structure and use throughout gint, is as follows. For a write:
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WRITING ---------------------.
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^ | | HW buffer
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Start writing | | Not full | full: start
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| | | transmission
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write(2) | v v
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--> IDLE ------------------> PENDING <------------- FLYING-WRITE
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^ ^ | DONE interrupt
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| DONE write(2) | |
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| interrupt | |
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| | | Data exhausted
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| sync(2): start | v
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FLYING-COMMIT <------------ IN-PROGRESS
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transmission
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Initially the operation is in the IDLE state. When a write(2) is issued, it
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interacts with hardware then transitions to the IN-PROGRESS state, where it
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remains for any subsequent write(2). A sync(2) will properly commit data to
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the hardware, finish the operation and return to the IDLE state.
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The FLYING-WRITE and FLYING-COMMIT states refer to waiting periods, after
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issuing hardware commands, during which hardware communicates. Usually an
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interrupt signals when hardware is ready to resume work.
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Note that in a series of write(2), hardware is only instructed to send data
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once the hardware buffer is full. Therefore, a write(2) might transition
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directly from IDLE or IN-PROGRESS, to PENDING, to IN-PROGRESS, without
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actually communicating with the outside world.
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The invariants and meaning for each state are as follow:
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State Characterization Description
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============================================================================
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IDLE type == ASYNCIO_NONE No I/O operation
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PENDING data_w && !flying_w \ Ready to write pending data
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&& round_size == 0
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WRITING round_size > 0 CPU/DMA write to HW in progress
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FLYING-WRITE flying_w && !committed_w HW transmission in progress
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IN-PROGRESS data_w != NULL && !flying_w Waiting for write(2) or sync(2)
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FLYING-COMMIT flying_w && committed_w HW commit in progress
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============================================================================
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For a read:
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IN interrupt
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--> IDLE-EMPTY --------------> IDLE-READY
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| \ | ^
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read(2) | \ Transaction read(2) | | Buffer full with
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| \ exhausted | | transaction not exhausted
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| '----<----------. | |
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| \ | |
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v IN interrupt \ v | .---. Read from
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WAITING ------------------> READING v hardware
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'---'
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On this diagram, the right side indicates the presence of data to read from
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hardware while the bottom side indicates a read(2) request by the user.
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Notice the diagonal arrow back to IDLE-EMPTY, which means that read(2) will
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always return at the end of a transaction even if the user-provided buffer
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is not full (to avoid waiting).
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The invariants and meaning for each state are as follow:
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State Characterization Description
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============================================================================
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IDLE-EMPTY type == ASYNCIO_NONE No I/O operation
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IDLE-READY !data_r && buffer_size > 0 Hardware waiting for us to read
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WAITING data_r && !buffer_size Waiting for further HW data
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READING round_size > 0 DMA/CPU read from HW in progress
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============================================================================
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States can be checked and transitioned with the API functions below. */
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enum { ASYNCIO_NONE, ASYNCIO_READ, ASYNCIO_WRITE };
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typedef struct
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{
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/** User-facing information **/
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/* Direction of I/O operation */
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uint8_t type;
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/* Whether the DMA should be used for hardware access */
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bool dma;
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/* Whether the data has been committed by sync(2) [write] */
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bool committed_w;
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/* Operation's unit size (meaning depends on hardware) */
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uint8_t unit_size;
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union {
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/* Address of data to transfer, incremented gradually [write] */
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void const *data_w;
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/* Address of buffer to store data to, incremented gradually [read] */
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void *data_r;
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};
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/* Size of data left to transfer / buffer space available */
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int size;
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/* Callback at the end of the current write, final commit, or read */
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gint_call_t callback;
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/** Hardware state information **/
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/* Size of data currently in the hardware buffer */
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uint16_t buffer_used;
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/* Size of data being read/written in the current round (which may itself
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be asynchronous if it's using the DMA) */
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uint16_t round_size;
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/* Hardware resource being used for access (meaning depends on hardware).
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Usually, this is assigned during hardware transactions, ie.:
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- During a write, a controller is assigned when leaving the IDLE state
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and returned when re-entering the IDLE state.
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- During a read, a controller is assigne when leaving the IDLE-EMPTY
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state and returned when re-entering the IDLE-EMPTY state. */
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uint8_t controller;
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/* Whether a hardware operation is in progress ("flying" write states) */
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bool flying_w;
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} asyncio_op_t;
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/* */
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#endif /* GINT_USB_ASYNCIO */
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118
src/usb/pipes.c
118
src/usb/pipes.c
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@ -6,6 +6,7 @@
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#include <string.h>
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#include "asyncio.h"
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#include "usb_private.h"
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#define USB SH7305_USB
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@ -173,39 +174,19 @@ static void fifo_unbind(fifo_t ct)
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/* Current operation waiting to be performed on each pipe. There are two
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possible states for a pipe's transfer data:
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-> Either there is a transfer going on, in which case (data != NULL),
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(size != 0), and (used) has no meaning.
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(size != 0), and (buffer_used) has no meaning.
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-> Either there is no transfer going on, and (data = NULL), (size = 0).
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A controller is assigned to t->ct when a write first occurs until the pipe
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is fully committed. (ct = NOF) indicates an unused pipe, while (ct != NOF)
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indicates that stuff has been written and is waiting a commit.
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A controller is assigned to t->controller when a write first occurs until
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the pipe is fully committed. (ct = NOF) indicates an unused pipe, while
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(ct != NOF) indicates that stuff has been written and is waiting a commit.
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Additionally, between a call to write_round() and the corresponding
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finish_write(), the (flying) attribute is set to a non-zero value indicating
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how many bytes are waiting for write completion. */
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struct transfer {
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/* Address of data to transfer next */
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void const *data;
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/* Size of data left to transfer */
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int size;
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/* Size of data currently in the FIFO (less than the FIFO capacity) */
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uint16_t used;
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/* Data sent in the last transfer not yet finished by finish_round() */
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uint16_t flying;
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/* Write size */
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uint8_t unit_size;
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/* Whether the data has been committed to a transfer */
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bool committed;
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/* Whether to use the DMA */
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bool dma;
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/* FIFO controller being used for this transfer */
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fifo_t ct;
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/* Callback to be invoked at the end of the current write or commit
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(both cannot exist at the same time) */
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gint_call_t callback;
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};
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finish_write(), the (round_size) attribute is set to a non-zero value
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indicating how many bytes are waiting for write completion. */
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/* Multi-round operations to be continued whenever buffers are ready */
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GBSS static struct transfer volatile pipe_transfers[10];
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GBSS static asyncio_op_t volatile pipe_transfers[10];
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void usb_pipe_init_transfers(void)
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{
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@ -229,11 +210,11 @@ static void write_32(uint32_t const *data, int size, uint32_t volatile *FIFO)
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GINLINE static bool pipe_busy(int pipe)
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{
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/* Multi-round write still not finished */
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if(pipe_transfers[pipe].data) return true;
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if(pipe_transfers[pipe].data_w) return true;
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/* Transfer in progress */
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if(pipe && !USB.PIPECTR[pipe-1].BSTS) return true;
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/* Callback for a just-finished transfer not yet called */
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if(pipe_transfers[pipe].flying) return true;
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if(pipe_transfers[pipe].round_size) return true;
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/* All good */
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return false;
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}
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@ -241,7 +222,8 @@ GINLINE static bool pipe_busy(int pipe)
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/* Size of a pipe's buffer area, in bytes */
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static int pipe_bufsize(int pipe)
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{
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if(pipe == 0) return USB.DCPMAXP.MXPS;
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if(pipe == 0)
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return USB.DCPMAXP.MXPS;
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USB.PIPESEL.PIPESEL = pipe;
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return (USB.PIPEBUF.BUFSIZE + 1) * 64;
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@ -252,15 +234,15 @@ static int pipe_bufsize(int pipe)
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This function is called when the final round of a transfer has completed,
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either by the handler of the BEMP interrupt or by the usb_commit_async()
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function if the pipe is being committed when empty. */
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static void finish_transfer(struct transfer volatile *t, int pipe)
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static void finish_transfer(asyncio_op_t volatile *t, int pipe)
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{
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/* Free the FIFO controller */
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fifo_unbind(t->ct);
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t->ct = NOF;
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fifo_unbind(t->controller);
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t->controller = NOF;
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/* Mark the transfer as unused */
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t->committed = false;
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t->used = 0;
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t->committed_w = false;
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t->buffer_used = 0;
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/* Disable the interrupt */
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if(pipe != 0)
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@ -278,22 +260,22 @@ static void finish_transfer(struct transfer volatile *t, int pipe)
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It the current write operation has finished with this round, this function
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invokes the write_async callback. */
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static void finish_round(struct transfer volatile *t, int pipe)
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static void finish_round(asyncio_op_t volatile *t, int pipe)
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{
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/* Update the pointer as a result of the newly-finished write */
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t->used += t->flying;
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t->data += t->flying;
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t->size -= t->flying;
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t->flying = 0;
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t->buffer_used += t->round_size;
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t->data_w += t->round_size;
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t->size -= t->round_size;
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t->round_size = 0;
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/* Account for auto-transfers */
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if(t->used == pipe_bufsize(pipe))
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t->used = 0;
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if(t->buffer_used == pipe_bufsize(pipe))
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t->buffer_used = 0;
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/* At the end, free the FIFO and invoke the callback. Hold the
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controller until the pipe is committed */
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if(t->size == 0) {
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t->data = NULL;
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t->data_w = NULL;
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gint_call(t->callback);
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}
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@ -305,9 +287,9 @@ static void finish_round(struct transfer volatile *t, int pipe)
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If this is a partial round (FIFO not going to be full), finish_round() is
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invoked after the write. Otherwise the FIFO is transmitted automatically and
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the BEMP handler will call finish_round() after the transfer. */
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static void write_round(struct transfer volatile *t, int pipe)
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static void write_round(asyncio_op_t volatile *t, int pipe)
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{
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fifo_t ct = t->ct;
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fifo_t ct = t->controller;
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void volatile *FIFO = NULL;
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if(ct == CF) FIFO = &USB.CFIFO;
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@ -316,9 +298,9 @@ static void write_round(struct transfer volatile *t, int pipe)
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fifo_bind(ct, pipe, FIFO_WRITE, t->unit_size);
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/* Amount of data that can be transferred in a single run */
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int available = pipe_bufsize(pipe) - (pipe == 0 ? 0 : t->used);
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int available = pipe_bufsize(pipe) - (pipe == 0 ? 0 : t->buffer_used);
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int size = min(t->size, available);
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t->flying = size;
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t->round_size = size;
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/* If this is a partial write (size < available), call finish_round()
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after the copy to notify the user that the pipe is ready. Otherwise,
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@ -340,14 +322,14 @@ static void write_round(struct transfer volatile *t, int pipe)
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int channel = (ct == D0F) ? 3 : 4;
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bool ok = dma_transfer_async(channel, block_size, size,
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t->data, DMA_INC, (void *)FIFO, DMA_FIXED, callback);
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t->data_w, DMA_INC, (void *)FIFO, DMA_FIXED, callback);
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if(!ok) USB_LOG("DMA async failed on channel %d!\n", channel);
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}
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else
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{
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if(t->unit_size == 1) write_8(t->data, size, FIFO);
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if(t->unit_size == 2) write_16(t->data, size >> 1, FIFO);
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if(t->unit_size == 4) write_32(t->data, size >> 2, FIFO);
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if(t->unit_size == 1) write_8(t->data_w, size, FIFO);
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if(t->unit_size == 2) write_16(t->data_w, size >> 1, FIFO);
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if(t->unit_size == 4) write_32(t->data_w, size >> 2, FIFO);
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if(partial) finish_round(t, pipe);
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}
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@ -359,22 +341,22 @@ int usb_write_async(int pipe, void const *data, int size, int unit_size,
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{
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if(pipe_busy(pipe)) return USB_WRITE_BUSY;
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struct transfer volatile *t = &pipe_transfers[pipe];
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asyncio_op_t volatile *t = &pipe_transfers[pipe];
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if(!data || !size) return 0;
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/* Re-use the controller from a previous write if there is one,
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otherwise try to get a new free one */
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/* TODO: usb_write_async(): TOC/TOU race on controller being free */
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fifo_t ct = t->ct;
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fifo_t ct = t->controller;
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if(ct == NOF) ct = fifo_find_available_controller(pipe);
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if(ct == NOF) return USB_WRITE_NOFIFO;
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t->data = data;
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t->data_w = data;
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t->size = size;
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t->unit_size = (pipe == 0) ? 1 : unit_size;
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t->dma = use_dma;
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t->committed = false;
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t->ct = ct;
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t->committed_w = false;
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t->controller = ct;
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t->callback = callback;
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/* Set up the Buffer Empty interrupt to refill the buffer when it gets
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@ -421,12 +403,12 @@ int usb_write_sync(int pipe, void const *data, int size, int unit, bool dma)
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int usb_commit_async(int pipe, gint_call_t callback)
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{
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struct transfer volatile *t = &pipe_transfers[pipe];
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asyncio_op_t volatile *t = &pipe_transfers[pipe];
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if(pipe_busy(pipe)) return USB_COMMIT_BUSY;
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if(t->ct == NOF) return USB_COMMIT_INACTIVE;
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if(t->controller == NOF) return USB_COMMIT_INACTIVE;
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t->committed = true;
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t->committed_w = true;
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t->callback = callback;
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/* TODO: Handle complex commits on the DCP */
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@ -438,17 +420,17 @@ int usb_commit_async(int pipe, gint_call_t callback)
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}
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/* Committing an empty pipe ends the transfer on the spot */
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if(t->used == 0)
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if(t->buffer_used == 0)
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{
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finish_transfer(t, pipe);
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return 0;
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}
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/* Set BVAL=1 and inform the BEMP handler of the commitment with the
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committed flag; the handler will invoke finish_transfer() */
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fifo_bind(t->ct, pipe, FIFO_WRITE, t->unit_size);
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if(t->ct == D0F) USB.D0FIFOCTR.BVAL = 1;
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if(t->ct == D1F) USB.D1FIFOCTR.BVAL = 1;
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committed_w flag; the handler will invoke finish_transfer() */
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fifo_bind(t->controller, pipe, FIFO_WRITE, t->unit_size);
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if(t->controller == D0F) USB.D0FIFOCTR.BVAL = 1;
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if(t->controller == D1F) USB.D1FIFOCTR.BVAL = 1;
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USB_LOG("[PIPE%d] Committed transfer\n", pipe);
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return 0;
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@ -489,9 +471,9 @@ void usb_commit_sync(int pipe)
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/* usb_pipe_write_bemp(): Callback for the BEMP interrupt on a pipe */
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void usb_pipe_write_bemp(int pipe)
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{
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struct transfer volatile *t = &pipe_transfers[pipe];
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asyncio_op_t volatile *t = &pipe_transfers[pipe];
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if(t->committed)
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if(t->committed_w)
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{
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finish_transfer(t, pipe);
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}
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@ -499,6 +481,6 @@ void usb_pipe_write_bemp(int pipe)
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{
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/* Finish a round; if there is more data, keep going */
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finish_round(t, pipe);
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if(t->data) write_round(t, pipe);
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if(t->data_w) write_round(t, pipe);
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}
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}
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