cpg: add overclock for SH3/SH4 fx-9860G and G-III (#23)
Co-authored-by: Slyvtt <pillot.sylvain@gmail.com>
This commit is contained in:
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736b58f205
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GPG Key ID:
1BBA026E13FC0495
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@ -68,28 +68,40 @@ enum {
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/* Combinations of hardware settings that are none of Ftune's levels */
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CLOCK_SPEED_UNKNOWN = 0,
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/* Ftune's 5 default overclock levels. The main settings are listed below,
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thoug many more are involved.
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On SH4 fx-9860G-likr:
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(Not supported yet)
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On the fx G-III series:
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(Not supported yet)
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/* Ftune's 5 default overclock levels. The main settings are listed
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below, though many more are involved.
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On SH3 fx-9860G-like:
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F1: CPU @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz [Similar to G-III default]
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F3: CPU @ 88 MHz
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F4: CPU @ 118 MHz [Fastest CPU option]
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F5: CPU @ 118 MHz [Reduced memory wait times]
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On SH4 fx-9860G-like:
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F1: CPU @ 29 MHz, BFC @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Similar to G-III default]
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F3: CPU @ 29 MHz, BFC @ 29 MHz [SH3 default]
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F4: CPU @ 118 MHz, BFC @ 59 MHz
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F5: CPU @ 236 MHz, BFC @ 118 MHz [Fastest option]
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On G-III / Graph 35+E II:
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F1: CPU @ 58 MHz, BFC @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [fx-CG 10/20 default]
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F3: CPU @ 29 MHz, BFC @ 29 MHz [SH3 default]
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F4: CPU @ 118 MHz, BFC @ 58 MHz
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F5: CPU @ 235 MHz, BFC @ 58 MHz [Fastest option]
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On fx-CG 10/20:
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F1: CPU @ 58 MHz, BFC @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Improved memory speed]
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F3: CPU @ 118 MHz, BFC @ 58 MHz [Faster than F2]
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F4: CPU @ 118 MHz, BFC @ 118 MHz [Fastest bus option]
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F5: CPU @ 191 MHz, BFC @ 94 MHz [Fastest CPU option]
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F1: CPU @ 58 MHz, BFC @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Improved memory speed]
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F3: CPU @ 118 MHz, BFC @ 58 MHz [Faster than F2]
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F4: CPU @ 118 MHz, BFC @ 118 MHz [Fastest bus option]
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F5: CPU @ 191 MHz, BFC @ 94 MHz [Fastest CPU option]
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On fx-CG 50:
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F1: CPU @ 116 MHz, BFC @ 58 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [fx-CG 10/20 default]
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F3: CPU @ 94 MHz, BFC @ 47 MHz [Clearly slow: F2 < F3 < F1]
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F4: CPU @ 232 MHz, BFC @ 58 MHz [Fastest CPU option]
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F5: CPU @ 189 MHz, BFC @ 94 MHz [Fastest bus option] */
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On fx-CG 50:
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F1: CPU @ 116 MHz, BFC @ 58 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Clearly slower: F2 < F3 < F1]
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F3: CPU @ 94 MHz, BFC @ 47 MHz [Clearly slower: F2 < F3 < F1]
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F4: CPU @ 232 MHz, BFC @ 58 MHz [Fastest CPU option]
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F5: CPU @ 189 MHz, BFC @ 94 MHz [Fastest bus option] */
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CLOCK_SPEED_F1 = 1,
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CLOCK_SPEED_F2 = 2,
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CLOCK_SPEED_F3 = 3,
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@ -100,7 +112,6 @@ enum {
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CLOCK_SPEED_DEFAULT = CLOCK_SPEED_F1,
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};
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#ifdef FXCG50
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/* clock_get_speed(): Determine the current clock speed
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This function compares the current hardware state with the settings for each
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@ -123,7 +134,6 @@ int clock_get_speed(void);
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Currently the clock speed is not reset during a world switch nor when
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leaving the add-in. */
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void clock_set_speed(int speed);
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#endif
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//---
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// Sleep functions
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@ -12,6 +12,80 @@ extern "C" {
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 But State Controller. Refer to:
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// Renesas SH7705 Group Hardware Manual
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// Section 7: Bus State Controller (BSC)
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//---
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typedef volatile lword_union(sh7705_bsc_CSnBCR_t,
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uint32_t :2;
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uint32_t IWW :2; /* Wait cycles for Write-Read and Write-Write */
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uint32_t :1;
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uint32_t IWRWD :2; /* Wait cycles for other-space Read-Write */
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uint32_t :1;
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uint32_t IWRWS :2; /* Wait cycles for same-space Read-Write */
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uint32_t :1;
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uint32_t IWRRD :2; /* Wait cycles for other-space Read-Read */
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uint32_t :1;
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uint32_t IWRRS :2; /* Wait cycles for same-space Read-Read */
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uint32_t :1;
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uint32_t TYPE :3; /* Memory type */
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uint32_t :1;
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uint32_t BSZ :2; /* Data bus size */
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uint32_t :9;
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);
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/* Warning: the layout of this register changes with n *and* with the memory
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type. This version is not exhaustive. Check the manual! */
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typedef volatile lword_union(sh7705_bsc_CSnWCR_t,
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uint32_t :13;
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uint32_t WW :3; /* Write access wait cycles */
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uint32_t :3;
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uint32_t SW :2; /* Wait from CSn/address to RD/WEn assertion */
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uint32_t WR :4; /* Access wait cycles */
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uint32_t WM :1; /* Whether to use external wait */
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uint32_t :4;
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uint32_t HW :2; /* Wait from RD/WEn to CSn/address negation */
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);
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typedef volatile struct
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{
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lword_union(CMNCR,
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uint32_t :24;
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uint32_t DMAIW :2; /* DMA single-address wait states */
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uint32_t DMAIWA :1; /* DMAIW wait states insertion method */
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uint32_t :1;
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uint32_t const ENDIAN :1; /* Global CPU endianness flag */
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uint32_t :1;
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uint32_t HIZMEM :1; /* High-Z memory Control*/
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uint32_t HIZCNT :1; /* High-Z Control*/
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);
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sh7705_bsc_CSnBCR_t CS0BCR;
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sh7705_bsc_CSnBCR_t CS2BCR;
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sh7705_bsc_CSnBCR_t CS3BCR;
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sh7705_bsc_CSnBCR_t CS4BCR;
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sh7705_bsc_CSnBCR_t CS5ABCR;
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sh7705_bsc_CSnBCR_t CS5BBCR;
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sh7705_bsc_CSnBCR_t CS6ABCR;
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sh7705_bsc_CSnBCR_t CS6BBCR;
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sh7705_bsc_CSnWCR_t CS0WCR;
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sh7705_bsc_CSnWCR_t CS2WCR;
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sh7705_bsc_CSnWCR_t CS3WCR;
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sh7705_bsc_CSnWCR_t CS4WCR;
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sh7705_bsc_CSnWCR_t CS5AWCR;
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sh7705_bsc_CSnWCR_t CS5BWCR;
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sh7705_bsc_CSnWCR_t CS6AWCR;
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sh7705_bsc_CSnWCR_t CS6BWCR;
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/* TODO: There are more registers (not involved in overclocking). */
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} GPACKED(4) sh7705_bsc_t;
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#define SH7705_BSC (*(sh7705_bsc_t *)0xa4fd0000)
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//---
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// SH7305 But State Controller. Refer to:
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// Renesas SH7730 Group Hardware Manual
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@ -32,6 +32,12 @@ typedef volatile struct
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uint16_t PFC :2; /* Peripheral clock divider */
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);
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byte_union(UCLKCR,
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uint8_t USSCS :2; /* Source Clock Selection Bit */
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uint8_t USBEN :1; /* USB On-Chip Oscillator Enable */
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uint8_t :5;
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);
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} GPACKED(4) sh7705_cpg_t;
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#define SH7705_CPG (*((sh7705_cpg_t *)0xffffff80))
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@ -0,0 +1,52 @@
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//---
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// gint:mpu:wdt - Watchdog Timer
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//---
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#ifndef GINT_MPU_WDT
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#define GINT_MPU_WDT
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 WatchDog Timer. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 10: "WatchDog Timer (WDT)"
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//---
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/* sh7705_wdt_t - Watch Dog Timer */
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typedef volatile struct
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{
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/* WDT registers are unique in access size; reads are performed with
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8-bit accesses, but writes are performed with 16-bit accesses. */
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union {
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uint8_t READ;
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uint16_t WRITE;
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} WTCNT;
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union {
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byte_union(READ,
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uint8_t TME :1; /* Timer Enable */
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uint8_t WTIT :1; /* Watchdog/Interval Select */
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uint8_t RSTS :1; /* Watchdog Reset Select */
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uint8_t WOVF :1; /* Watchdog Overflow Flag */
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uint8_t IOVF :1; /* Interval Overflow Flag */
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uint8_t CKS :3; /* Clock Select */
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);
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uint16_t WRITE;
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} WTCSR;
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} sh7705_wdt_t;
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#define SH7705_WDT (*((sh7705_wdt_t *)0xffffff84))
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_WDT */
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@ -27,7 +27,6 @@ const clock_frequency_t *clock_freq(void)
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//---
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#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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#define CPG SH7705_CPG
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void sh7705_probe(void)
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{
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@ -41,35 +40,23 @@ void sh7705_probe(void)
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int ckio = xtal * pll2;
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/* This signal is multiplied by the PLL1 circuit */
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int pll1 = CPG.FRQCR.STC + 1;
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int pll1 = SH7705_CPG.FRQCR.STC + 1;
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/* Iphi and Pphi have dividers (Bphi is always equal to CKIO) */
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int idiv = CPG.FRQCR.IFC;
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int pdiv = CPG.FRQCR.PFC;
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/* Fill in the setting structure */
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/* Fill in the setting structure. Iϕ and Pϕ have dividers, while Bϕ is
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always equal to CKIO. */
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freq.PLL1 = pll1;
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freq.PLL2 = pll2;
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freq.Bphi_div = 1;
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freq.Iphi_div = idiv + 1;
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freq.Pphi_div = pdiv + 1;
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/* Deduce the frequency of the main clocks. This value is ckio/3 */
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int ckio_3 = 9830400;
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/* Exchange the setting values 2 and 3 (corresponding to /3 and /4)
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This means that /1, /2, /4 are now 0, 1, 2, which is perfect for a
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quick bit shift */
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idiv = idiv ^ (idiv >> 1);
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pdiv = pdiv ^ (pdiv >> 1);
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freq.Iphi_div = SH7705_CPG.FRQCR.IFC + 1;
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freq.Pphi_div = SH7705_CPG.FRQCR.PFC + 1;
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/* Deduce the frequency of the main clocks */
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freq.CKIO_f = ckio;
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freq.Bphi_f = ckio;
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freq.Iphi_f = (idiv == 3) ? ckio_3 : ckio >> idiv;
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freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv;
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freq.Iphi_f = (ckio * pll1) / freq.Iphi_div;
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freq.Pphi_f = (ckio * pll1) / freq.Pphi_div;
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}
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#undef CPG
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#endif /* FX9860G and platform-agnostic */
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//---
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@ -134,9 +121,7 @@ static void configure(void)
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{
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/* Disable spread spectrum in SSGSCR */
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if(isSH4())
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{
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SH7305_CPG.SSCGCR.SSEN = 0;
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}
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cpg_compute_freq();
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}
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@ -147,18 +132,16 @@ static void configure(void)
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static void hsave(cpg_state_t *s)
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{
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if(isSH4()) {
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if(isSH4())
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s->SSCGCR = SH7305_CPG.SSCGCR.lword;
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cpg_get_overclock_setting(&s->speed);
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}
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cpg_get_overclock_setting(&s->speed);
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}
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static void hrestore(cpg_state_t const *s)
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{
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if(isSH4()) {
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if(isSH4())
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SH7305_CPG.SSCGCR.lword = s->SSCGCR;
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cpg_set_overclock_setting(&s->speed);
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}
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cpg_set_overclock_setting(&s->speed);
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}
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gint_driver_t drv_cpg = {
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@ -14,137 +14,285 @@
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#include <gint/hardware.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/bsc.h>
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#include <gint/mpu/wdt.h>
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//---
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// Low-level clock speed access
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//---
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#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(!isSH4())
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return;
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s->FLLFRQ = CPG.FLLFRQ.lword;
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s->FRQCR = CPG.FRQCR.lword;
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s->CS0BCR = BSC.CS0BCR.lword;
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s->CS0WCR = BSC.CS0WCR.lword;
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s->CS2BCR = BSC.CS2BCR.lword;
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s->CS2WCR = BSC.CS2WCR.lword;
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s->CS3BCR = BSC.CS3BCR.lword;
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s->CS3WCR = BSC.CS3WCR.lword;
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s->CS5aBCR = BSC.CS5ABCR.lword;
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s->CS5aWCR = BSC.CS5AWCR.lword;
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}
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void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(!isSH4())
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return;
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BSC.CS0WCR.WR = 11; /* 18 cycles */
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CPG.FLLFRQ.lword = s->FLLFRQ;
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CPG.FRQCR.lword = s->FRQCR;
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CPG.FRQCR.KICK = 1;
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while(CPG.LSTATS != 0) {}
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BSC.CS0BCR.lword = s->CS0BCR;
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BSC.CS0WCR.lword = s->CS0WCR;
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BSC.CS2BCR.lword = s->CS2BCR;
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BSC.CS2WCR.lword = s->CS2WCR;
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BSC.CS3BCR.lword = s->CS3BCR;
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BSC.CS3WCR.lword = s->CS3WCR;
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if(BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = s->CS5aBCR;
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BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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#define SH7305_SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SH7305_SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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//---
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// Predefined clock speeds
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//---
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#ifdef FXCG50
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/* SH7305 CPG */
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#define SH4_PLL_32x 0b011111
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#define SH4_PLL_26x 0b011001
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#define SH4_PLL_16x 0b001111
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#define SH4_DIV_2 0
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#define SH4_DIV_4 1
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#define SH4_DIV_8 2
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#define SH4_DIV_16 3
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#define SH4_DIV_32 4
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#define PLL_32x 0b011111
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#define PLL_26x 0b011001
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#define PLL_16x 0b001111
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#define DIV_2 0
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#define DIV_4 1
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#define DIV_8 2
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#define DIV_16 3
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#define DIV_32 4
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/* SH7705-like CPG */
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#define SH3_PLL_1x 0
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#define SH3_PLL_2x 1
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#define SH3_PLL_3x 2
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#define SH3_PLL_4x 3
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#define SH3_DIV_1 0
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#define SH3_DIV_2 1
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#define SH3_DIV_3 2
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#define SH3_DIV_4 3
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static struct cpg_overclock_setting settings_cg50[5] = {
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(isSH3()) {
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s->FLLFRQ = -1;
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s->FRQCR = SH7705_CPG.FRQCR.word;
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s->CS0BCR = SH7705_BSC.CS0BCR.lword;
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s->CS0WCR = SH7705_BSC.CS0WCR.lword;
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s->CS2BCR = SH7705_BSC.CS2BCR.lword;
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s->CS2WCR = SH7705_BSC.CS2WCR.lword;
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s->CS3BCR = SH7705_BSC.CS3BCR.lword;
|
||||
s->CS3WCR = SH7705_BSC.CS3WCR.lword;
|
||||
s->CS5aBCR = SH7705_BSC.CS5ABCR.lword;
|
||||
s->CS5aWCR = SH7705_BSC.CS5AWCR.lword;
|
||||
}
|
||||
else {
|
||||
s->FLLFRQ = SH7305_CPG.FLLFRQ.lword;
|
||||
s->FRQCR = SH7305_CPG.FRQCR.lword;
|
||||
|
||||
s->CS0BCR = SH7305_BSC.CS0BCR.lword;
|
||||
s->CS0WCR = SH7305_BSC.CS0WCR.lword;
|
||||
s->CS2BCR = SH7305_BSC.CS2BCR.lword;
|
||||
s->CS2WCR = SH7305_BSC.CS2WCR.lword;
|
||||
s->CS3BCR = SH7305_BSC.CS3BCR.lword;
|
||||
s->CS3WCR = SH7305_BSC.CS3WCR.lword;
|
||||
s->CS5aBCR = SH7305_BSC.CS5ABCR.lword;
|
||||
s->CS5aWCR = SH7305_BSC.CS5AWCR.lword;
|
||||
}
|
||||
}
|
||||
|
||||
void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
|
||||
{
|
||||
if(isSH3()) {
|
||||
SH7705_WDT.WTCNT.WRITE = 0;
|
||||
SH7705_WDT.WTCSR.WRITE = 0x65;
|
||||
SH7705_CPG.FRQCR.word = s->FRQCR | 0x1000;
|
||||
SH7705_BSC.CS0BCR.lword = s->CS0BCR;
|
||||
SH7705_BSC.CS0WCR.lword = s->CS0WCR;
|
||||
SH7705_BSC.CS2BCR.lword = s->CS2BCR;
|
||||
SH7705_BSC.CS2WCR.lword = s->CS2WCR;
|
||||
SH7705_BSC.CS3BCR.lword = s->CS3BCR;
|
||||
SH7705_BSC.CS3WCR.lword = s->CS3WCR;
|
||||
SH7705_BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||
SH7705_BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||
}
|
||||
else {
|
||||
SH7305_BSC.CS0WCR.WR = 11; /* 18 cycles */
|
||||
|
||||
SH7305_CPG.FLLFRQ.lword = s->FLLFRQ;
|
||||
SH7305_CPG.FRQCR.lword = s->FRQCR;
|
||||
SH7305_CPG.FRQCR.KICK = 1;
|
||||
while(SH7305_CPG.LSTATS != 0) {}
|
||||
|
||||
SH7305_BSC.CS0BCR.lword = s->CS0BCR;
|
||||
SH7305_BSC.CS0WCR.lword = s->CS0WCR;
|
||||
SH7305_BSC.CS2BCR.lword = s->CS2BCR;
|
||||
SH7305_BSC.CS2WCR.lword = s->CS2WCR;
|
||||
SH7305_BSC.CS3BCR.lword = s->CS3BCR;
|
||||
SH7305_BSC.CS3WCR.lword = s->CS3WCR;
|
||||
|
||||
if(SH7305_BSC.CS3WCR.A3CL == 1)
|
||||
*SH7305_SDMR3_CL2 = 0;
|
||||
else
|
||||
*SH7305_SDMR3_CL3 = 0;
|
||||
|
||||
SH7305_BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||
SH7305_BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef FX9860G
|
||||
|
||||
static struct cpg_overclock_setting const settings_fx9860g_sh3[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = 0x0F011112,
|
||||
.CS0BCR = 0x36DA0400,
|
||||
.CS2BCR = 0x36DA3400,
|
||||
.CS3BCR = 0x36DB4400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x000003C0,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
{ .FRQCR = 0x1001,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000340,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
{ .FRQCR = (SH3_PLL_2x<<8)+(SH3_DIV_1<<4)+SH3_DIV_2,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000240,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
{ .FRQCR = (SH3_PLL_3x<<8)+(SH3_DIV_1<<4)+SH3_DIV_3,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x000002C0,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
{ .FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000440,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
{ .FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
|
||||
.CS0BCR = 0x02480400,
|
||||
.CS2BCR = 0x02483400,
|
||||
.CS3BCR = 0x36DB0600,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000000C0,
|
||||
.CS2WCR = 0x000100C0,
|
||||
.CS3WCR = 0x00000500,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
};
|
||||
|
||||
static struct cpg_overclock_setting settings_cg20[5] = {
|
||||
static struct cpg_overclock_setting const settings_fx9860g_sh4[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = 0x0F202203,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000005C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x24920200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000003C0,
|
||||
.CS2WCR = 0x000302C0,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
};
|
||||
|
||||
static struct cpg_overclock_setting const settings_g35pe2[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = 0x0F112213,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x000001C0,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00031340 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x24920200,
|
||||
.CS0WCR = 0x00000140,
|
||||
.CS2WCR = 0x00000140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00000D41 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00031B40 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004384,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x14900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x224A0200,
|
||||
.CS0WCR = 0x000001C0,
|
||||
.CS2WCR = 0x00020140,
|
||||
.CS3WCR = 0x000024D0,
|
||||
.CS5aWCR = 0x00031B40 },
|
||||
};
|
||||
|
||||
#endif /* FX9860G */
|
||||
|
||||
#ifdef FXCG50
|
||||
|
||||
static struct cpg_overclock_setting const settings_prizm[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = 0x0F102203,
|
||||
|
|
@ -158,7 +306,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_8<<20)+(DIV_16<<12)+(DIV_16<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_16<<12)+(SH4_DIV_16<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x04900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -169,7 +317,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x24900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -180,7 +328,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_32,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_32,
|
||||
.CS0BCR = 0x44900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -191,7 +339,7 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_16,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x34900400,
|
||||
.CS2BCR = 0x04903400,
|
||||
.CS3BCR = 0x24924400,
|
||||
|
|
@ -202,35 +350,125 @@ static struct cpg_overclock_setting settings_cg20[5] = {
|
|||
.CS5aWCR = 0x00010240 },
|
||||
};
|
||||
|
||||
static struct cpg_overclock_setting *get_settings(void)
|
||||
static struct cpg_overclock_setting const settings_fxcg50[5] = {
|
||||
/* CLOCK_SPEED_F1 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = 0x0F011112,
|
||||
.CS0BCR = 0x36DA0400,
|
||||
.CS2BCR = 0x36DA3400,
|
||||
.CS3BCR = 0x36DB4400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x000003C0,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F2 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000340,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F3 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000240,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F4 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x000002C0,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
/* CLOCK_SPEED_F5 */
|
||||
{ .FLLFRQ = 0x00004000 + 900,
|
||||
.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_8,
|
||||
.CS0BCR = 0x24920400,
|
||||
.CS2BCR = 0x24923400,
|
||||
.CS3BCR = 0x24924400,
|
||||
.CS5aBCR = 0x17DF0400,
|
||||
.CS0WCR = 0x00000440,
|
||||
.CS2WCR = 0x000003C0,
|
||||
.CS3WCR = 0x000024D1,
|
||||
.CS5aWCR = 0x000203C1 },
|
||||
};
|
||||
|
||||
#endif /* FXCG50 */
|
||||
|
||||
static struct cpg_overclock_setting const *get_settings(void)
|
||||
{
|
||||
if(gint[HWCALC] == HWCALC_FXCG50)
|
||||
return settings_cg50;
|
||||
#ifdef FX9860G
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH3)
|
||||
return settings_fx9860g_sh3;
|
||||
if(gint[HWCALC] == HWCALC_FX9860G_SH4)
|
||||
return settings_fx9860g_sh4;
|
||||
if(gint[HWCALC] == HWCALC_G35PE2)
|
||||
return settings_g35pe2;
|
||||
#endif /* FX9860G */
|
||||
|
||||
#ifdef FXCG50
|
||||
if(gint[HWCALC] == HWCALC_PRIZM)
|
||||
return settings_cg20;
|
||||
return settings_prizm;
|
||||
if(gint[HWCALC] == HWCALC_FXCG50)
|
||||
return settings_fxcg50;
|
||||
#endif /* FXCG50 */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int clock_get_speed(void)
|
||||
{
|
||||
struct cpg_overclock_setting *settings = get_settings();
|
||||
struct cpg_overclock_setting const *settings = get_settings();
|
||||
if(!settings)
|
||||
return CLOCK_SPEED_UNKNOWN;
|
||||
|
||||
for(int i = 0; i < 5; i++) {
|
||||
struct cpg_overclock_setting *s = &settings[i];
|
||||
if(isSH3()) {
|
||||
for(int i = 0; i < 5; i++) {
|
||||
struct cpg_overclock_setting const *s = &settings[i];
|
||||
|
||||
if(CPG.FLLFRQ.lword == s->FLLFRQ
|
||||
&& CPG.FRQCR.lword == s->FRQCR
|
||||
&& BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
return CLOCK_SPEED_F1 + i;
|
||||
if(SH7705_CPG.FRQCR.word == (s->FRQCR | 0x1000)
|
||||
&& SH7705_BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& SH7705_BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& SH7705_BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& SH7705_BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& SH7705_BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& SH7705_BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& SH7705_BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& SH7705_BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
return CLOCK_SPEED_F1 + i;
|
||||
}
|
||||
}
|
||||
else {
|
||||
for(int i = 0; i < 5; i++) {
|
||||
struct cpg_overclock_setting const *s = &settings[i];
|
||||
|
||||
if(SH7305_CPG.FLLFRQ.lword == s->FLLFRQ
|
||||
&& SH7305_CPG.FRQCR.lword == s->FRQCR
|
||||
&& SH7305_BSC.CS0BCR.lword == s->CS0BCR
|
||||
&& SH7305_BSC.CS2BCR.lword == s->CS2BCR
|
||||
&& SH7305_BSC.CS3BCR.lword == s->CS3BCR
|
||||
&& SH7305_BSC.CS5ABCR.lword == s->CS5aBCR
|
||||
&& SH7305_BSC.CS0WCR.lword == s->CS0WCR
|
||||
&& SH7305_BSC.CS2WCR.lword == s->CS2WCR
|
||||
&& SH7305_BSC.CS3WCR.lword == s->CS3WCR
|
||||
&& SH7305_BSC.CS5AWCR.lword == s->CS5aWCR)
|
||||
return CLOCK_SPEED_F1 + i;
|
||||
}
|
||||
}
|
||||
|
||||
return CLOCK_SPEED_UNKNOWN;
|
||||
|
|
@ -243,11 +481,11 @@ void clock_set_speed(int level)
|
|||
if(clock_get_speed() == level)
|
||||
return;
|
||||
|
||||
struct cpg_overclock_setting *settings = get_settings();
|
||||
struct cpg_overclock_setting const *settings = get_settings();
|
||||
if(!settings)
|
||||
return;
|
||||
|
||||
struct cpg_overclock_setting *s = &settings[level - CLOCK_SPEED_F1];
|
||||
struct cpg_overclock_setting const *s = &settings[level - CLOCK_SPEED_F1];
|
||||
uint32_t old_Pphi = clock_freq()->Pphi_f;
|
||||
|
||||
/* Wait for asynchronous tasks to complete */
|
||||
|
|
@ -269,5 +507,3 @@ void clock_set_speed(int level)
|
|||
|
||||
cpu_atomic_end();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue