Untested INTC module in /include/modules/interrupts.h
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lephe
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@ -464,6 +464,178 @@ typedef mod_intc_irq_7305_t mod_intc_intreq00_7305_t;
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typedef mod_intc_irq_7305_t mod_intc_intmsk00_7305_t;
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typedef mod_intc_irq_7305_t mod_intc_intmskclr00_7305_t;
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/*
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mod_intc_masks_7305_t
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A set of bits to mask individual interrupts.
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- Masking interrupts is realized by writing 1 to IMRs ;
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- Clearing masks is realized by writing 1 to IMCRs ;
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Using the wrong register set, such as writing 0 to IMRs to clear a
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mask, will be ignored and have no effect. Reading from IMCRs yields an
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undefined value.
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*/
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typedef struct
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{
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byte_union(IMR0,
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uint :1;
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uint TUNI1_2 :1; /* TMU1 overflow interrupts */
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uint TUNI1_1 :1;
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uint TUNI1_0 :1;
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uint SDHII3 :1; /* SD Card Host 1 interrupts */
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uint SDHII2 :1;
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uint SDHII1 :1;
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uint SDHII0 :1;
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);
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pad(3);
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byte_union(IMR1,
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uint :4;
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uint DEI3 :1; /* DMAC0A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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);
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pad(3);
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byte_union(IMR2,
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uint :7;
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uint SCIFA0 :1; /* Asynchronous Serial interrupts */
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);
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pad(3);
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byte_union(IMR3,
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uint DEI3 :1; /* DMAC1A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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uint :4;
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);
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pad(3);
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byte_union(IMR4,
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uint :1;
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uint TUNI0_2 :1; /* TMU0 overflow interrupts */
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uint TUNI0_1 :1;
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uint TUNI0_0 :1;
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uint :3;
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uint LCDCI :1; /* LCD Controller Interrupt */
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);
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pad(3);
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byte_union(IMR5,
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uint KEYI :1; /* Key Interface */
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uint DADERR :1; /* DMAC0B interrupts */
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uint DEI5 :1;
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uint DEI4 :1;
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uint :1;
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uint SCIF2 :1; /* Serial Communication Interface */
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uint SCIF1 :1;
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uint SCIF0 :1;
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);
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pad(3);
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byte_union(IMR6,
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uint :2;
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uint :1;
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uint SCIFA4 :1; /* SCIFA4 interrupt */
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uint :1;
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uint :1;
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uint MSIOFI0 :1; /* Clock-synchronized SCIF channel 0 */
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uint MSIOFI1 :1; /* Clock-synchronized SCIF channel 1 */
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);
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pad(3);
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uint8_t IMR7;
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pad(3);
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byte_union(IMR8,
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uint SDHII3 :1; /* SD Card Host 0 interrupts */
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uint SDHII2 :1;
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uint SDHII1 :1;
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uint SDHII0 :1;
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uint :2;
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uint SCFIA5 :1; /* SCIFA5 interrupt */
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uint FSI :1; /* FIFO-Buffered Serial Interface */
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);
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pad(3);
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byte_union(IMR9,
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uint :3;
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uint CMTI :1; /* Compare Match Timer Interrupt */
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uint :1;
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uint USI1 :1; /* USB1 */
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uint USI0 :1; /* USB0 */
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uint :1;
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);
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pad(3);
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byte_union(IMR10,
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uint :1;
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uint DADERR :1; /* DMAC1B interrupts */
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uint DEI5 :1;
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uint DEI4 :1;
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uint :1;
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uint ATI :1; /* RTC Alarm interrupt */
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uint PRI :1; /* RTC Periodic interrupt */
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uint CUI :1; /* RTC Carry interrupt */
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);
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pad(3);
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byte_union(IMR11,
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uint :5;
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uint TPUI :1; /* Timer-Pulse Unit */
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uint :2;
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);
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pad(3);
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uint8_t IMR12;
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char gap2[15];
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} __attribute__((packed)) mod_intc_masks_7305_t;
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/*
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mod_intc_userimask_7305_t
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User Interrupt Mask: Specifies the minimum required level for
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interrupts to be accepted.
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WARNING: Writing to this register requires the eight upper bits of the
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operand (ie. the new value of USERIMASK) to be 0xa5; otherwise, the
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write is ignored. To modify the value of this register, do not access
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the bit field directly, backup the variable and modify it:
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void set_user_imask(int new_level)
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{
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mod_intc_userimask_7305_t mask = *(INTC._7305.USERIMASK);
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mask._a5 = 0xa5;
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mask.UIMASK = new_level & 0x0f;
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*(INTC._7305.USERIMASK) = mask;
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}
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*/
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typedef struct
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{
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lword_union(,
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uint _a5 :8; /* Always set to 0xa5 before writing */
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uint :16;
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uint UIMASK :4; /* User Interrupt Mask Level */
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uint :4;
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);
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} __attribute__((packed, aligned(4))) mod_intc_userimask_7305_t;
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/*
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mod_intc_nmifcr_7305_t
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NMI Flag Control Register: Indicates the state of the NMI pin and the
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NMI interrupt request.
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*/
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typedef struct
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{
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byte_union(,
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uint const NMIL :1; /* NMI Interupt Level */
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uint :14;
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uint NMIFL :1; /* NMI Interrupt Request Flag */
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);
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} __attribute__((packed, aligned(2))) mod_intc_nmifcr_7305_t;
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/*
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mod_intc_7305_t
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Finally the whole interrupt controller.
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@ -480,10 +652,34 @@ typedef struct
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/* Interrupt mask & mask clear registers */
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volatile mod_intc_intmsk00_7305_t *INTMSK00;
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// volatile mod_intc_masks_7305_t *masks;
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volatile mod_intc_masks_7305_t *masks;
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volatile mod_intc_intmskclr00_7305_t *INTMSKCLR00;
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// volatile mod_intc_masks_clear_7305_t *masks_clear;
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volatile mod_intc_masks_7305_t *masks_clear;
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/* Other registers */
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volatile mod_intc_intreq00_7305_t *INTREQ00;
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volatile mod_intc_userimask_7305_t *USERIMASK;
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volatile mod_intc_nmifcr_7305_t *NMIFCR;
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} mod_intc_7305_t;
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//---
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// Platform-independent structures.
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// Unfortunately there is nothing here. Users willing to manage interrupts
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// using the INTC register will have to handle explicitely both platforms.
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//---
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/*
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mod_intc_t
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Interrupt Controller.
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*/
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typedef union
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{
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mod_intc_7705_t _7705;
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mod_intc_7305_t _7305;
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} __attribute__((packed)) mod_intc_t;
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#endif // _MODULE_INTERRUPTS
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@ -1,5 +1,6 @@
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#include <modules/timer.h>
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#include <modules/rtc.h>
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#include <modules/interrupts.h>
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#include <stddef.h>
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#include <mpu.h>
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@ -15,6 +16,7 @@
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mod_tmu_t TMU;
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mod_rtc_t RTC;
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mod_intc_t INTC;
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@ -24,7 +26,6 @@ mod_rtc_t RTC;
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static void mod_init_7705(void)
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{
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/*
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INTC._7705.iprs.IPRA = (void *)0xfffffee2;
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INTC._7705.iprs.IPRB = (void *)0xfffffee4;
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INTC._7705.iprs.IPRC = (void *)0xa4000016;
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@ -41,7 +42,6 @@ static void mod_init_7705(void)
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INTC._7705.IRR0 = (void *)0xa4000004;
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INTC._7705.IRR1 = (void *)0xa4000006;
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INTC._7705.IRR2 = (void *)0xa4000008;
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*/
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TMU.timers[0] = (void *)0xfffffe94;
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TMU.timers[1] = (void *)0xfffffea0;
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@ -56,7 +56,17 @@ static void mod_init_7705(void)
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static void mod_init_7305(void)
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{
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// INTC._7305.iprs = (void *)0xa4080000;
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INTC._7305.ICR0 = (void *)0xa4140000;
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INTC._7305.ICR1 = (void *)0xa414001c;
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INTC._7305.INTPRI00 = (void *)0xa4140010;
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INTC._7305.iprs = (void *)0xa4080000;
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INTC._7305.INTMSK00 = (void *)0xa4140044;
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INTC._7305.masks = (void *)0xa4080080;
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INTC._7305.INTMSKCLR00 = (void *)0xa4140064;
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INTC._7305.masks_clear = (void *)0xa40800c0;
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INTC._7305.INTREQ00 = (void *)0xa4140024;
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INTC._7305.USERIMASK = (void *)0xa4700000;
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INTC._7305.NMIFCR = (void *)0xa41400c0;
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TMU.timers[0] = (void *)0xa4490008;
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TMU.timers[1] = (void *)0xa4490014;
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