diff --git a/src/cpg/cpg.c b/src/cpg/cpg.c index c50fa93..4ecd7c8 100644 --- a/src/cpg/cpg.c +++ b/src/cpg/cpg.c @@ -26,8 +26,8 @@ const clock_frequency_t *clock_freq(void) // SH7705 Clock signals //--- -#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50)) -#define CPG SH7705_CPG +//#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50)) +//#define CPGSH3 SH7705_CPG void sh7705_probe(void) { @@ -41,11 +41,11 @@ void sh7705_probe(void) int ckio = xtal * pll2; /* This signal is multiplied by the PLL1 circuit */ - int pll1 = CPG.FRQCR.STC + 1; + int pll1 = SH7705_CPG.FRQCR.STC + 1; /* Iphi and Pphi have dividers (Bphi is always equal to CKIO) */ - int idiv = CPG.FRQCR.IFC; - int pdiv = CPG.FRQCR.PFC; + int idiv = SH7705_CPG.FRQCR.IFC; + int pdiv = SH7705_CPG.FRQCR.PFC; /* Fill in the setting structure */ freq.PLL1 = pll1; @@ -69,33 +69,33 @@ void sh7705_probe(void) freq.Pphi_f = (pdiv == 3) ? ckio_3 : ckio >> pdiv; } -#undef CPG -#endif /* FX9860G and platform-agnostic */ +//#undef CPG +//#endif /* FX9860G and platform-agnostic */ //--- // SH7305 clock signals //--- -#define CPG SH7305_CPG +//#define CPGSH4 SH7305_CPG static void sh7305_probe(void) { /* The meaning of the PLL setting on SH7305 differs from the documentation of SH7224; the value must not be doubled. */ - int pll = CPG.FRQCR.STC + 1; + int pll = SH7305_CPG.FRQCR.STC + 1; freq.PLL = pll; /* The FLL ratio is the value of the setting, halved if SELXM=1 */ - int fll = CPG.FLLFRQ.FLF; - if(CPG.FLLFRQ.SELXM == 1) fll >>= 1; + int fll = SH7305_CPG.FLLFRQ.FLF; + if(SH7305_CPG.FLLFRQ.SELXM == 1) fll >>= 1; freq.FLL = fll; /* On SH7724, the divider ratio is given by 1 / (setting + 1), but on the SH7305 it is 1 / (2^setting + 1). */ - int divb = CPG.FRQCR.BFC; - int divi = CPG.FRQCR.IFC; - int divp = CPG.FRQCR.P1FC; + int divb = SH7305_CPG.FRQCR.BFC; + int divi = SH7305_CPG.FRQCR.IFC; + int divp = SH7305_CPG.FRQCR.P1FC; freq.Bphi_div = 1 << (divb + 1); freq.Iphi_div = 1 << (divi + 1); @@ -103,8 +103,8 @@ static void sh7305_probe(void) /* Deduce the input frequency of divider 1 */ int base = 32768; - if(CPG.PLLCR.FLLE) base *= fll; - if(CPG.PLLCR.PLLE) base *= pll; + if(SH7305_CPG.PLLCR.FLLE) base *= fll; + if(SH7305_CPG.PLLCR.PLLE) base *= pll; /* And the frequency of all other input clocks */ freq.RTCCLK_f = 32768; @@ -113,7 +113,7 @@ static void sh7305_probe(void) freq.Pphi_f = base >> (divp + 1); } -#undef CPG +//#undef CPG //--- @@ -124,10 +124,14 @@ void cpg_compute_freq(void) { /* This avoids warnings about sh7705_probe() being undefined when building for fxcg50 */ + + /* #if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50)) isSH3() ? sh7705_probe() : #endif sh7305_probe(); + */ + isSH3() ? sh7705_probe() : sh7305_probe(); } static void configure(void) diff --git a/src/cpg/overclock.c b/src/cpg/overclock.c index 6c18193..a5f74f7 100644 --- a/src/cpg/overclock.c +++ b/src/cpg/overclock.c @@ -16,12 +16,14 @@ #include #include +/* #define CPG SH7305_CPG #define BSC SH7305_BSC -#define CPGSH3 SH7705_CPG -#define BSCSH3 SH7705_BSC -#define WDTSH3 SH7705_WDT +#define SH7705_CPG SH7705_CPG +#define SH7705_BSC SH7705_BSC +#define SH7705_WDT SH7705_WDT +*/ //--- // Low-level clock speed access @@ -62,31 +64,31 @@ void cpg_get_overclock_setting(struct cpg_overclock_setting *s) if(isSH3()) { s->FLLFRQ = 0xFFFFFFF; // not used for SH3 MPUs - s->FRQCR = CPGSH3.FRQCR.word; + s->FRQCR = (uint32_t) SH7705_CPG.FRQCR.word; - s->CS0BCR = BSCSH3.CS0BCR.lword; - s->CS0WCR = BSCSH3.CS0WCR.lword; - s->CS2BCR = BSCSH3.CS2BCR.lword; - s->CS2WCR = BSCSH3.CS2WCR.lword; - s->CS3BCR = BSCSH3.CS3BCR.lword; - s->CS3WCR = BSCSH3.CS3WCR.lword; - s->CS5aBCR = BSCSH3.CS5ABCR.lword; - s->CS5aWCR = BSCSH3.CS5AWCR.lword; + s->CS0BCR = SH7705_BSC.CS0BCR.lword; + s->CS0WCR = SH7705_BSC.CS0WCR.lword; + s->CS2BCR = SH7705_BSC.CS2BCR.lword; + s->CS2WCR = SH7705_BSC.CS2WCR.lword; + s->CS3BCR = SH7705_BSC.CS3BCR.lword; + s->CS3WCR = SH7705_BSC.CS3WCR.lword; + s->CS5aBCR = SH7705_BSC.CS5ABCR.lword; + s->CS5aWCR = SH7705_BSC.CS5AWCR.lword; } if(isSH4()) { - s->FLLFRQ = CPG.FLLFRQ.lword; - s->FRQCR = CPG.FRQCR.lword; + s->FLLFRQ = SH7305_CPG.FLLFRQ.lword; + s->FRQCR = SH7305_CPG.FRQCR.lword; - s->CS0BCR = BSC.CS0BCR.lword; - s->CS0WCR = BSC.CS0WCR.lword; - s->CS2BCR = BSC.CS2BCR.lword; - s->CS2WCR = BSC.CS2WCR.lword; - s->CS3BCR = BSC.CS3BCR.lword; - s->CS3WCR = BSC.CS3WCR.lword; - s->CS5aBCR = BSC.CS5ABCR.lword; - s->CS5aWCR = BSC.CS5AWCR.lword; + s->CS0BCR = SH7305_BSC.CS0BCR.lword; + s->CS0WCR = SH7305_BSC.CS0WCR.lword; + s->CS2BCR = SH7305_BSC.CS2BCR.lword; + s->CS2WCR = SH7305_BSC.CS2WCR.lword; + s->CS3BCR = SH7305_BSC.CS3BCR.lword; + s->CS3WCR = SH7305_BSC.CS3WCR.lword; + s->CS5aBCR = SH7305_BSC.CS5ABCR.lword; + s->CS5aWCR = SH7305_BSC.CS5AWCR.lword; } return; @@ -96,42 +98,42 @@ void cpg_set_overclock_setting(struct cpg_overclock_setting const *s) { if(isSH3()) { - WDTSH3.WTCNT.WRITE = 0; - WDTSH3.WTCNT.WRITE = 0x65; - CPGSH3.FRQCR.word = 0x1000 | s->FRQCR; - BSCSH3.CS0BCR.lword = s->CS0BCR; - BSCSH3.CS0WCR.lword = s->CS0WCR; - BSCSH3.CS2BCR.lword = s->CS2BCR; - BSCSH3.CS2WCR.lword = s->CS2WCR; - BSCSH3.CS3BCR.lword = s->CS3BCR; - BSCSH3.CS3WCR.lword = s->CS3WCR; - BSCSH3.CS5ABCR.lword = s->CS5aBCR; - BSCSH3.CS5AWCR.lword = s->CS5aWCR; + SH7705_WDT.WTCNT.WRITE = 0; + SH7705_WDT.WTCNT.WRITE = 0x65; + SH7705_CPG.FRQCR.word = 0x1000 | (uint16_t) s->FRQCR; + SH7705_BSC.CS0BCR.lword = s->CS0BCR; + SH7705_BSC.CS0WCR.lword = s->CS0WCR; + SH7705_BSC.CS2BCR.lword = s->CS2BCR; + SH7705_BSC.CS2WCR.lword = s->CS2WCR; + SH7705_BSC.CS3BCR.lword = s->CS3BCR; + SH7705_BSC.CS3WCR.lword = s->CS3WCR; + SH7705_BSC.CS5ABCR.lword = s->CS5aBCR; + SH7705_BSC.CS5AWCR.lword = s->CS5aWCR; } if(isSH4()) { - BSC.CS0WCR.WR = 11; /* 18 cycles */ + SH7305_BSC.CS0WCR.WR = 11; /* 18 cycles */ - CPG.FLLFRQ.lword = s->FLLFRQ; - CPG.FRQCR.lword = s->FRQCR; - CPG.FRQCR.KICK = 1; - while(CPG.LSTATS != 0) {} + SH7305_CPG.FLLFRQ.lword = s->FLLFRQ; + SH7305_CPG.FRQCR.lword = s->FRQCR; + SH7305_CPG.FRQCR.KICK = 1; + while(SH7305_CPG.LSTATS != 0) {} - BSC.CS0BCR.lword = s->CS0BCR; - BSC.CS0WCR.lword = s->CS0WCR; - BSC.CS2BCR.lword = s->CS2BCR; - BSC.CS2WCR.lword = s->CS2WCR; - BSC.CS3BCR.lword = s->CS3BCR; - BSC.CS3WCR.lword = s->CS3WCR; + SH7305_BSC.CS0BCR.lword = s->CS0BCR; + SH7305_BSC.CS0WCR.lword = s->CS0WCR; + SH7305_BSC.CS2BCR.lword = s->CS2BCR; + SH7305_BSC.CS2WCR.lword = s->CS2WCR; + SH7305_BSC.CS3BCR.lword = s->CS3BCR; + SH7305_BSC.CS3WCR.lword = s->CS3WCR; - if(BSC.CS3WCR.A3CL == 1) + if(SH7305_BSC.CS3WCR.A3CL == 1) *SDMR3_CL2 = 0; else *SDMR3_CL3 = 0; - BSC.CS5ABCR.lword = s->CS5aBCR; - BSC.CS5AWCR.lword = s->CS5aWCR; + SH7305_BSC.CS5ABCR.lword = s->CS5aBCR; + SH7305_BSC.CS5AWCR.lword = s->CS5aWCR; } return; @@ -255,7 +257,6 @@ static struct cpg_overclock_setting settings_prizm[5] = { .CS5aWCR = 0x00010240 }, }; - /*settings for the fx9860G SH3 based*/ static struct cpg_overclock_setting settings_fx9860g_sh3[5] = { /* CLOCK_SPEED_F1 */ @@ -459,15 +460,15 @@ int clock_get_speed(void) for(int i = 0; i < 5; i++) { struct cpg_overclock_setting *s = &settings[i]; - if(CPGSH3.FRQCR.word == s->FRQCR // FRQCR is a uint16_t for SH3 - && BSCSH3.CS0BCR.lword == s->CS0BCR - && BSCSH3.CS2BCR.lword == s->CS2BCR - && BSCSH3.CS3BCR.lword == s->CS3BCR - && BSCSH3.CS5ABCR.lword == s->CS5aBCR - && BSCSH3.CS0WCR.lword == s->CS0WCR - && BSCSH3.CS2WCR.lword == s->CS2WCR - && BSCSH3.CS3WCR.lword == s->CS3WCR - && BSCSH3.CS5AWCR.lword == s->CS5aWCR) + if(SH7705_CPG.FRQCR.word == (uint16_t) s->FRQCR // FRQCR is a uint16_t for SH3 + && SH7705_BSC.CS0BCR.lword == s->CS0BCR + && SH7705_BSC.CS2BCR.lword == s->CS2BCR + && SH7705_BSC.CS3BCR.lword == s->CS3BCR + && SH7705_BSC.CS5ABCR.lword == s->CS5aBCR + && SH7705_BSC.CS0WCR.lword == s->CS0WCR + && SH7705_BSC.CS2WCR.lword == s->CS2WCR + && SH7705_BSC.CS3WCR.lword == s->CS3WCR + && SH7705_BSC.CS5AWCR.lword == s->CS5aWCR) return CLOCK_SPEED_F1 + i; } } @@ -477,16 +478,16 @@ int clock_get_speed(void) for(int i = 0; i < 5; i++) { struct cpg_overclock_setting *s = &settings[i]; - if(CPG.FLLFRQ.lword == s->FLLFRQ - && CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4 - && BSC.CS0BCR.lword == s->CS0BCR - && BSC.CS2BCR.lword == s->CS2BCR - && BSC.CS3BCR.lword == s->CS3BCR - && BSC.CS5ABCR.lword == s->CS5aBCR - && BSC.CS0WCR.lword == s->CS0WCR - && BSC.CS2WCR.lword == s->CS2WCR - && BSC.CS3WCR.lword == s->CS3WCR - && BSC.CS5AWCR.lword == s->CS5aWCR) + if(SH7305_CPG.FLLFRQ.lword == s->FLLFRQ + && SH7305_CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4 + && SH7305_BSC.CS0BCR.lword == s->CS0BCR + && SH7305_BSC.CS2BCR.lword == s->CS2BCR + && SH7305_BSC.CS3BCR.lword == s->CS3BCR + && SH7305_BSC.CS5ABCR.lword == s->CS5aBCR + && SH7305_BSC.CS0WCR.lword == s->CS0WCR + && SH7305_BSC.CS2WCR.lword == s->CS2WCR + && SH7305_BSC.CS3WCR.lword == s->CS3WCR + && SH7305_BSC.CS5AWCR.lword == s->CS5aWCR) return CLOCK_SPEED_F1 + i; } }