From fdadb0dd71d18357ccbeb85e628d09d5b0073f65 Mon Sep 17 00:00:00 2001 From: Lephe Date: Tue, 12 Apr 2022 16:23:18 +0100 Subject: [PATCH] mpu: rename FRQCRA into FRQCR --- include/gint/mpu/cpg.h | 2 +- src/cpg/cpg.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/gint/mpu/cpg.h b/include/gint/mpu/cpg.h index fc14cd2..a9bafdf 100644 --- a/include/gint/mpu/cpg.h +++ b/include/gint/mpu/cpg.h @@ -47,7 +47,7 @@ typedef volatile struct documentation. */ typedef volatile struct { - lword_union(FRQCRA, + lword_union(FRQCR, uint32_t KICK :1; /* Flush FRQCRA modifications */ uint32_t :1; uint32_t STC :6; /* PLL multiplication [*] */ diff --git a/src/cpg/cpg.c b/src/cpg/cpg.c index 21a30ac..a822e5a 100644 --- a/src/cpg/cpg.c +++ b/src/cpg/cpg.c @@ -82,7 +82,7 @@ static void sh7305_probe(void) { /* The meaning of the PLL setting on SH7305 differs from the documentation of SH7224; the value must not be doubled. */ - int pll = CPG.FRQCRA.STC + 1; + int pll = CPG.FRQCR.STC + 1; freq.PLL = pll; /* The FLL ratio is the value of the setting, halved if SELXM=1 */ @@ -93,9 +93,9 @@ static void sh7305_probe(void) /* On SH7724, the divider ratio is given by 1 / (setting + 1), but on the SH7305 it is 1 / (2^setting + 1). */ - int divb = CPG.FRQCRA.BFC; - int divi = CPG.FRQCRA.IFC; - int divp = CPG.FRQCRA.P1FC; + int divb = CPG.FRQCR.BFC; + int divi = CPG.FRQCR.IFC; + int divp = CPG.FRQCR.P1FC; freq.Bphi_div = 1 << (divb + 1); freq.Iphi_div = 1 << (divi + 1);