From 71816fbcb0a54e3c837a9c3ed0629f702b94e7a8 Mon Sep 17 00:00:00 2001 From: Slyvtt Date: Sun, 27 Nov 2022 22:20:07 +0100 Subject: [PATCH 1/4] added SCIF and PFC description for SH7305 --- include/gint/mpu/pfc.h | 180 ++++++++++++++++++++++++++++++++++++++++ include/gint/mpu/scif.h | 108 ++++++++++++++++++++++++ include/gint/serial.h | 38 +++++++++ src/scif/scif.c | 78 +++++++++++++++++ 4 files changed, 404 insertions(+) create mode 100644 include/gint/mpu/scif.h create mode 100644 include/gint/serial.h create mode 100644 src/scif/scif.c diff --git a/include/gint/mpu/pfc.h b/include/gint/mpu/pfc.h index a1c3fe0..d8aa71c 100644 --- a/include/gint/mpu/pfc.h +++ b/include/gint/mpu/pfc.h @@ -79,6 +79,186 @@ typedef volatile struct // TODO: Document the SH7305 Pin Function Controller //--- +typedef volatile word_union( sh7305_Port_Control_Register_t, + uint16_t P7MD :2; + uint16_t P6MD :2; + uint16_t P5MD :2; + uint16_t P4MD :2; + uint16_t P3MD :2; + uint16_t P2MD :2; + uint16_t P1MD :2; + uint16_t P0MD :2; +); + +typedef volatile byte_union( sh7305_port_data_register_t, + uint8_t P7DT :1; + uint8_t P6DT :1; + uint8_t P5DT :1; + uint8_t P4DT :1; + uint8_t P3DT :1; + uint8_t P2DT :1; + uint8_t P1DT :1; + uint8_t P0DT :1; +); + +typedef volatile word_union( sh7305_pin_select_register_t, + uint16_t PS15 :1; + uint16_t PS14 :1; + uint16_t PS13 :1; + uint16_t PS12 :1; + uint16_t PS11 :1; + uint16_t PS10 :1; + uint16_t PS9 :1; + uint16_t PS8 :1; + uint16_t PS7 :1; + uint16_t PS6 :1; + uint16_t PS5 :1; + uint16_t PS4 :1; + uint16_t PS3 :1; + uint16_t PS2 :1; + uint16_t PS1 :1; + uint16_t PS0 :1; +); + +typedef volatile word_union( sh7305_IO_buffer_hiz_control_register_t, + uint16_t HIZ15 :1; + uint16_t HIZ14 :1; + uint16_t HIZ13 :1; + uint16_t HIZ12 :1; + uint16_t HIZ11 :1; + uint16_t HIZ10 :1; + uint16_t HIZ9 :1; + uint16_t HIZ8 :1; + uint16_t HIZ7 :1; + uint16_t HIZ6 :1; + uint16_t HIZ5 :1; + uint16_t HIZ4 :1; + uint16_t HIZ3 :1; + uint16_t HIZ2 :1; + uint16_t HIZ1 :1; + uint16_t HIZ0 :1; +); + +typedef volatile word_union( sh7305_module_function_select_register_t, + uint16_t MSEL15 :1; + uint16_t MSEL14 :1; + uint16_t MSEL13 :1; + uint16_t MSEL12 :1; + uint16_t MSEL11 :1; + uint16_t MSEL10 :1; + uint16_t MSEL9 :1; + uint16_t MSEL8 :1; + uint16_t MSEL7 :1; + uint16_t MSEL6 :1; + uint16_t MSEL5 :1; + uint16_t MSEL4 :1; + uint16_t MSEL3 :1; + uint16_t MSEL2 :1; + uint16_t MSEL1 :1; + uint16_t MSEL0 :1; +); + +typedef volatile word_union( sh7305_IO_buffer_drive_control_register_t, + uint16_t DRV15 :1; + uint16_t DRV14 :1; + uint16_t DRV13 :1; + uint16_t DRV12 :1; + uint16_t DRV11 :1; + uint16_t DRV10 :1; + uint16_t DRV9 :1; + uint16_t DRV8 :1; + uint16_t DRV7 :1; + uint16_t DRV6 :1; + uint16_t DRV5 :1; + uint16_t DRV4 :1; + uint16_t DRV3 :1; + uint16_t DRV2 :1; + uint16_t DRV1 :1; + uint16_t DRV0 :1; +); + + +typedef volatile struct +{ + // List of all PORT CONTROL REGISTERS (PCRs) + sh7305_Port_Control_Register_t PACR; + sh7305_Port_Control_Register_t PBCR; + sh7305_Port_Control_Register_t PCCR; + sh7305_Port_Control_Register_t PDCR; + sh7305_Port_Control_Register_t PECR; + sh7305_Port_Control_Register_t PFCR; + sh7305_Port_Control_Register_t PGCR; + sh7305_Port_Control_Register_t PHCR; + sh7305_Port_Control_Register_t PJCR; + sh7305_Port_Control_Register_t PKCR; + sh7305_Port_Control_Register_t PLCR; + sh7305_Port_Control_Register_t PMCR; + sh7305_Port_Control_Register_t PNCR; + sh7305_Port_Control_Register_t PQCR; + sh7305_Port_Control_Register_t PRCR; + sh7305_Port_Control_Register_t PSCR; + sh7305_Port_Control_Register_t PTCR; + sh7305_Port_Control_Register_t PUCR; + sh7305_Port_Control_Register_t PVCR; + sh7305_Port_Control_Register_t PWCR; + sh7305_Port_Control_Register_t PXCR; + sh7305_Port_Control_Register_t PYCR; + sh7305_Port_Control_Register_t PZCR; + + // List of all PORT DATA REGISTERS (PDRs) + sh7305_port_data_register_t PADR; + sh7305_port_data_register_t PBDR; + sh7305_port_data_register_t PCDR; + sh7305_port_data_register_t PDDR; + sh7305_port_data_register_t PEDR; + sh7305_port_data_register_t PFDR; + sh7305_port_data_register_t PGDR; + sh7305_port_data_register_t PHDR; + sh7305_port_data_register_t PJDR; + sh7305_port_data_register_t PKDR; + sh7305_port_data_register_t PLDR; + sh7305_port_data_register_t PMDR; + sh7305_port_data_register_t PNDR; + sh7305_port_data_register_t PQDR; + sh7305_port_data_register_t PRDR; + sh7305_port_data_register_t PSDR; + sh7305_port_data_register_t PTDR; + sh7305_port_data_register_t PUDR; + sh7305_port_data_register_t PVDR; + sh7305_port_data_register_t PWDR; + sh7305_port_data_register_t PXDR; + sh7305_port_data_register_t PYDR; + sh7305_port_data_register_t PZDR; + + // List of all IO BUFFER HI-Z CONTROL REGISTERS (HIZCRs) + sh7305_IO_buffer_hiz_control_register_t HIZCRA; + sh7305_IO_buffer_hiz_control_register_t HIZCRB; + sh7305_IO_buffer_hiz_control_register_t HIZCRC; + sh7305_IO_buffer_hiz_control_register_t HIZCRD; + + // List of all MODULE FUNCTION SELECT REGISTERS (MSELs) + sh7305_module_function_select_register_t MSELCRA; + sh7305_module_function_select_register_t MSELCRB; + + // PULL-UP CONTROL REGISTER (PULCR) + word_union( PULCR, + uint16_t PUL15 :1; + uint16_t reserved : 15; + ); + + // List of all IO BUFFER DRIVE CONTROL REGISTERS (DRVCRs) + sh7305_IO_buffer_drive_control_register_t DRVCRA; + sh7305_IO_buffer_drive_control_register_t DRVCRB; + sh7305_IO_buffer_drive_control_register_t DRVCRC; + +} sh7305_pfc_t; + +#define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100)) + + + + + #ifdef __cplusplus } #endif diff --git a/include/gint/mpu/scif.h b/include/gint/mpu/scif.h new file mode 100644 index 0000000..96110f9 --- /dev/null +++ b/include/gint/mpu/scif.h @@ -0,0 +1,108 @@ +//--- +// gint:mpu:scif - Serial Communication Interface with FIFO (SCIF) +//--- + +#ifndef GINT_MPU_SCIF +#define GINT_MPU_SCIF + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + +typedef volatile struct +{ + // Serial Mode + word_union(SCSMR, + uint16_t :8; //Reserved + uint16_t CA :1; //Communication Mode. + uint16_t CHR :1; //Character Length. + uint16_t PE :1; //Parity Enable + uint16_t OE :1; //Parity Mode + uint16_t STOP :1; //Bit Stop Length + uint16_t :1; //Reserved + uint16_t CKS :2; //Clock Select + ); + pad(0x2); + + // Serial Bit Rate + uint8_t SCBRD; //set the bit rate of serial transmission/reception in relation to the operating clock of the baud rate generator + pad(0x3); + + // Serial Control + word_union(SCSCR, + uint16_t :8; //Reserved + uint16_t TIE :1; //Transmit Interrupt Enable + uint16_t RIE :1; //Receive Interrupt Enable + uint16_t TE :1; //Transmit Enable + uint16_t RE :1; //Receive Mode + uint16_t REIE :1; //Receive Error Interrupt Enable + uint16_t :1; //Reserved + uint16_t CKE :2; //Clock Enable + ); + pad(0x2); + + // Serial Transmit data + uint8_t SCFTD; // FIFO for serial transmit data + pad(0x3); + + // Serial Status + word_union(SCFSR, + uint16_t PERC :4; //Number of Parity Errors + uint16_t FERC :4; //Number of Framing Errors + uint16_t ER :1; //Receive Error + uint16_t TEND :1; //Transmit End + uint16_t TDFE :1; //Transmit FIFO Data Empty + uint16_t BRK :1; //Break Detection + uint16_t FER :1; //Framing Error Indication + uint16_t PER :1; //Parity Error Indication + uint16_t RDF :1; //Receive FIFO Data Full + uint16_t DR :1; //Received data Ready + ); + pad(0x2); + + // Serial Receive data + uint8_t SCFRD; // FIFO for serial received data + pad(0x3); + + // Serial FIFO Control + word_union(SCFCR, + uint16_t :8; //Reserved + uint16_t RTRG :2; //Receive FIFO Data Trigger + uint16_t TTRG :2; //Transmit FIFO Data Trigger + uint16_t :1; //Reserved + uint16_t TFRST :1; //Transmit FIFO Data Register Reset + uint16_t RFRST :1; //Receive FIFO Data Register Reset + uint16_t LOOP :1; //Loopback Test + ); + pad(0x2); + + // Serial FIFO Count + word_union(SCFDR, + uint16_t :3; //Reserved + uint16_t TFDC :5; //Number of Data Bytes in Transmit FIFO + uint16_t :3; //Reserved + uint16_t RFDC :5; //Number of Data Bytes in Receive FIFO + ); + pad(0x2); + + // Serial Line Status + word_union(SCLSR, + uint16_t :15; //Reserved + uint16_t ORER :1; //Overrun Error + ); + pad(0x2); + +} GPACKED(4) sh7305_scif_t; + +#define SH7305_SCIF (*((sh7305_scif_t *)0x0xa4410000)) + + +#ifdef __cplusplus +} +#endif + +#endif /* GINT_MPU_SCIF */ \ No newline at end of file diff --git a/include/gint/serial.h b/include/gint/serial.h new file mode 100644 index 0000000..e7d7074 --- /dev/null +++ b/include/gint/serial.h @@ -0,0 +1,38 @@ +//--- +// gint:serial - Serial operation +//--- + +#ifndef GINT_SERIAL +#define GINT_SERIAL + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + + + +int gint_serial_read_one_byte(unsigned char *dest); + +int gint_serial_write_one_byte(unsigned char byte); + +int gint_serial_write_bytes(unsigned char *src, int size); + +int gint_serial_clear_receive_buffer(void); + +int gint_serial_clear_transmit_buffer(void); + +int gint_serial_open(unsigned char *conf); + +int gint_serial_close(int mode); + + +#ifdef __cplusplus +} +#endif + +#endif /* GINT_SERIAL */ \ No newline at end of file diff --git a/src/scif/scif.c b/src/scif/scif.c new file mode 100644 index 0000000..171645e --- /dev/null +++ b/src/scif/scif.c @@ -0,0 +1,78 @@ +//--- +// gint:serial - Serial operation +//--- + +#include + +#define SCIF SH7305_SCIF + + +int gint_serial_read_one_byte(unsigned char *dest) +{ + +}; + +int gint_serial_write_one_byte(unsigned char byte) +{ + +}; + +int gint_serial_write_bytes(unsigned char *src, int size) +{ + +}; + +int gint_serial_clear_receive_buffer(void) +{ + +}; + +int gint_serial_clear_transmit_buffer(void) +{ + +}; + +int gint_serial_open(unsigned char *conf) +{ + SCIF.SCSCR.TE=0b0; + SCIF.SCSCR.RE=0b0; + SCIF.SCSCR.TIE=0b0; + SCIF.SCSCR.RIE=0b0; + + SCIF.SCFCR.TFRST=0b1; + SCIF.SCFCR.RFRST=0b1; + + SCIF.SCLCR.ORER=0b0; + SCIF.SCFSR.ER=0b0; + SCIF.SCFSR.DR=0b0; + SCIF.SCFSR.BRK=0b0; + + SCIF.SCSCR.CKE=0b01; //set to internal clock + + SCIF.SCSMR.CA = 0b1; // clock synchronous mode + SCIF.SCSMR.CHR = 0b0; // 8bits length for data + SCIF.SCSMR.PE = 0b0; // Parity bit not set + SCIF.SCSMR.OE = 0b0; // just cleared, no effect as no parity is set + SCIF.SCSMR.STOP = 0b0; // not effect in synchronous mode + SCIF.SCSMR.CKS = 0b00; // 00=Pphi, 01=Pphi/4, 10=Pphi/16, 11=Pphi/64 + + SCIF.SCFCR.RTRG = 0b11; + SCIF.SCFCR.TTRG = 0b11; + SCIF.SCFCR.RFRST = 0b0; + SCIF.SCFCR.TFRST = 0b0; + + //PFC setting for external pins used + //SCK, TXD, RXD + + SCIF.SCSCR.TE=0b1; + SCIF.SCSCR.RE=0b1; + SCIF.SCSCR.TIE=0b1; + SCIF.SCSCR.RIE=0b1; + SCIF.SCSCR.REIE=0b1; + +}; + +int gint_serial_close(int mode) +{ + +}; \ No newline at end of file -- 2.45.0 From 779caa371fe5abfb2b31a2cbdc03fec2c2a5ee77 Mon Sep 17 00:00:00 2001 From: Slyvtt Date: Tue, 29 Nov 2022 21:04:09 +0100 Subject: [PATCH 2/4] sync PFC.h with Yatis and SH7724 doc --- include/gint/mpu/pfc.h | 56 ++++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 16 deletions(-) diff --git a/include/gint/mpu/pfc.h b/include/gint/mpu/pfc.h index d8aa71c..2bb94ba 100644 --- a/include/gint/mpu/pfc.h +++ b/include/gint/mpu/pfc.h @@ -197,13 +197,6 @@ typedef volatile struct sh7305_Port_Control_Register_t PQCR; sh7305_Port_Control_Register_t PRCR; sh7305_Port_Control_Register_t PSCR; - sh7305_Port_Control_Register_t PTCR; - sh7305_Port_Control_Register_t PUCR; - sh7305_Port_Control_Register_t PVCR; - sh7305_Port_Control_Register_t PWCR; - sh7305_Port_Control_Register_t PXCR; - sh7305_Port_Control_Register_t PYCR; - sh7305_Port_Control_Register_t PZCR; // List of all PORT DATA REGISTERS (PDRs) sh7305_port_data_register_t PADR; @@ -222,24 +215,54 @@ typedef volatile struct sh7305_port_data_register_t PQDR; sh7305_port_data_register_t PRDR; sh7305_port_data_register_t PSDR; - sh7305_port_data_register_t PTDR; - sh7305_port_data_register_t PUDR; - sh7305_port_data_register_t PVDR; - sh7305_port_data_register_t PWDR; - sh7305_port_data_register_t PXDR; - sh7305_port_data_register_t PYDR; - sh7305_port_data_register_t PZDR; + + sh7305_Port_Control_Register_t PTCR; + sh7305_Port_Control_Register_t PUCR; + sh7305_Port_Control_Register_t PVCR; + + //Missing ports ? + //sh7305_Port_Control_Register_t PWCR; + //sh7305_Port_Control_Register_t PXCR; + //sh7305_Port_Control_Register_t PYCR; + //sh7305_Port_Control_Register_t PZCR; + pad( 0x08 ); + + // List of all PIN SELECT REGISTERS (PSELs) + sh7305_pin_select_register_t PSELA; + sh7305_pin_select_register_t PSELB; + sh7305_pin_select_register_t PSELC; + sh7305_pin_select_register_t PSELD; + sh7305_pin_select_register_t PSELE; // List of all IO BUFFER HI-Z CONTROL REGISTERS (HIZCRs) sh7305_IO_buffer_hiz_control_register_t HIZCRA; sh7305_IO_buffer_hiz_control_register_t HIZCRB; sh7305_IO_buffer_hiz_control_register_t HIZCRC; - sh7305_IO_buffer_hiz_control_register_t HIZCRD; + + // the next one is not clearly listed, can be aither PSELF or HIZCRD so we skip it with pad + //sh7305_pin_select_register_t PSELF; + //sh7305_IO_buffer_hiz_control_register_t HIZCRD; + pad( 0x02 ); + + sh7305_port_data_register_t PTDR; + sh7305_port_data_register_t PUDR; + sh7305_port_data_register_t PVDR; + + //sh7305_port_data_register_t PWDR; + //sh7305_port_data_register_t PXDR; + //sh7305_port_data_register_t PYDR; + //sh7305_port_data_register_t PZDR; + pad( 0x08 ); + + + pad( 20 ); // jump from address 0xa405016c to 0xa4050180 + // List of all MODULE FUNCTION SELECT REGISTERS (MSELs) sh7305_module_function_select_register_t MSELCRA; sh7305_module_function_select_register_t MSELCRB; - + +/* // PULL-UP CONTROL REGISTER (PULCR) word_union( PULCR, uint16_t PUL15 :1; @@ -251,6 +274,7 @@ typedef volatile struct sh7305_IO_buffer_drive_control_register_t DRVCRB; sh7305_IO_buffer_drive_control_register_t DRVCRC; +*/ } sh7305_pfc_t; #define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100)) -- 2.45.0 From 9ba216d1de6f218abd8f44bbb2ad48a11c2330a3 Mon Sep 17 00:00:00 2001 From: Slyvtt Date: Tue, 29 Nov 2022 21:13:05 +0100 Subject: [PATCH 3/4] some cleaning in pfc.h --- include/gint/mpu/pfc.h | 13 +------------ include/gint/serial.h | 2 ++ src/scif/scif.c | 35 ----------------------------------- 3 files changed, 3 insertions(+), 47 deletions(-) diff --git a/include/gint/mpu/pfc.h b/include/gint/mpu/pfc.h index 2bb94ba..23a362d 100644 --- a/include/gint/mpu/pfc.h +++ b/include/gint/mpu/pfc.h @@ -248,6 +248,7 @@ typedef volatile struct sh7305_port_data_register_t PUDR; sh7305_port_data_register_t PVDR; + //Missing ports ? //sh7305_port_data_register_t PWDR; //sh7305_port_data_register_t PXDR; //sh7305_port_data_register_t PYDR; @@ -262,19 +263,7 @@ typedef volatile struct sh7305_module_function_select_register_t MSELCRA; sh7305_module_function_select_register_t MSELCRB; -/* - // PULL-UP CONTROL REGISTER (PULCR) - word_union( PULCR, - uint16_t PUL15 :1; - uint16_t reserved : 15; - ); - // List of all IO BUFFER DRIVE CONTROL REGISTERS (DRVCRs) - sh7305_IO_buffer_drive_control_register_t DRVCRA; - sh7305_IO_buffer_drive_control_register_t DRVCRB; - sh7305_IO_buffer_drive_control_register_t DRVCRC; - -*/ } sh7305_pfc_t; #define SH7305_PFC (*((sh7305_pfc_t *)0xa4050100)) diff --git a/include/gint/serial.h b/include/gint/serial.h index e7d7074..3b9c1e3 100644 --- a/include/gint/serial.h +++ b/include/gint/serial.h @@ -15,6 +15,8 @@ extern "C" { #include +// Prototypes of functions expected to appear in the serial module +// aims at reproducing the OS syscalls int gint_serial_read_one_byte(unsigned char *dest); diff --git a/src/scif/scif.c b/src/scif/scif.c index 171645e..93396c2 100644 --- a/src/scif/scif.c +++ b/src/scif/scif.c @@ -34,41 +34,6 @@ int gint_serial_clear_transmit_buffer(void) int gint_serial_open(unsigned char *conf) { - SCIF.SCSCR.TE=0b0; - SCIF.SCSCR.RE=0b0; - SCIF.SCSCR.TIE=0b0; - SCIF.SCSCR.RIE=0b0; - - SCIF.SCFCR.TFRST=0b1; - SCIF.SCFCR.RFRST=0b1; - - SCIF.SCLCR.ORER=0b0; - SCIF.SCFSR.ER=0b0; - SCIF.SCFSR.DR=0b0; - SCIF.SCFSR.BRK=0b0; - - SCIF.SCSCR.CKE=0b01; //set to internal clock - - SCIF.SCSMR.CA = 0b1; // clock synchronous mode - SCIF.SCSMR.CHR = 0b0; // 8bits length for data - SCIF.SCSMR.PE = 0b0; // Parity bit not set - SCIF.SCSMR.OE = 0b0; // just cleared, no effect as no parity is set - SCIF.SCSMR.STOP = 0b0; // not effect in synchronous mode - SCIF.SCSMR.CKS = 0b00; // 00=Pphi, 01=Pphi/4, 10=Pphi/16, 11=Pphi/64 - - SCIF.SCFCR.RTRG = 0b11; - SCIF.SCFCR.TTRG = 0b11; - SCIF.SCFCR.RFRST = 0b0; - SCIF.SCFCR.TFRST = 0b0; - - //PFC setting for external pins used - //SCK, TXD, RXD - - SCIF.SCSCR.TE=0b1; - SCIF.SCSCR.RE=0b1; - SCIF.SCSCR.TIE=0b1; - SCIF.SCSCR.RIE=0b1; - SCIF.SCSCR.REIE=0b1; }; -- 2.45.0 From fbdefcf7b32609bd50aaad8e03811a638fed47e3 Mon Sep 17 00:00:00 2001 From: Slyvtt Date: Sat, 3 Dec 2022 12:55:11 +0100 Subject: [PATCH 4/4] Prepare SCIF PFC description for SH7305 + prototypes of methods --- include/gint/mpu/pfc.h | 2 +- include/gint/serial.h | 1 + src/scif/scif.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/gint/mpu/pfc.h b/include/gint/mpu/pfc.h index 23a362d..d7c6e98 100644 --- a/include/gint/mpu/pfc.h +++ b/include/gint/mpu/pfc.h @@ -256,7 +256,7 @@ typedef volatile struct pad( 0x08 ); - pad( 20 ); // jump from address 0xa405016c to 0xa4050180 + pad( 0x12 ); // jump from address 0xa405016e to 0xa4050180 // List of all MODULE FUNCTION SELECT REGISTERS (MSELs) diff --git a/include/gint/serial.h b/include/gint/serial.h index 3b9c1e3..ce68deb 100644 --- a/include/gint/serial.h +++ b/include/gint/serial.h @@ -10,6 +10,7 @@ extern "C" { #endif #include +#include #include #include #include diff --git a/src/scif/scif.c b/src/scif/scif.c index 93396c2..ea555ee 100644 --- a/src/scif/scif.c +++ b/src/scif/scif.c @@ -5,6 +5,7 @@ #include #define SCIF SH7305_SCIF +#define PFC SH7305_PFC int gint_serial_read_one_byte(unsigned char *dest) -- 2.45.0