360 lines
8.9 KiB
C
360 lines
8.9 KiB
C
#include <gint/hardware.h>
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#include <gint/mpu/dma.h>
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#include <gint/mpu/power.h>
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#include <gint/mpu/intc.h>
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#include <gint/intc.h>
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#include <gint/dma.h>
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#include <gint/drivers.h>
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#include <gint/drivers/states.h>
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#include <gint/clock.h>
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#include <gint/exc.h>
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#include <gint/cpu.h>
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#define DMA SH7305_DMA
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#define POWER SH7305_POWER
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typedef volatile sh7305_dma_channel_t channel_t;
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/* Callbacks for all channels */
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static gint_call_t dma_callbacks[6] = { 0 };
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/* Sleep blocking flags for all channels */
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static bool dma_sleep_blocking[6] = { 0 };
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/* ICS for dma_channel_wait() for all channels */
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static cpu_csleep_t *dma_wait_ics[6] = { 0 };
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/* dma_channel(): Get address of a DMA channel */
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static channel_t *dma_channel(int channel)
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{
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channel_t *addr[6] = {
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&DMA.DMA0, &DMA.DMA1, &DMA.DMA2,
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&DMA.DMA3, &DMA.DMA4, &DMA.DMA5,
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};
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return ((uint)channel >= 6 ? NULL : addr[channel]);
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}
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/* dma_translate(): Translate virtual address to DMA-suitable form */
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static uint32_t dma_translate(void const *address)
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{
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uint32_t a = (uint32_t)address;
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/* Preserve RS addresses (as of SH7724 Reference, 11.2.2) */
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if(a >= 0xfd800000 && a < 0xfd800800)
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return a;
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/* Translate virtual addresses to IL memory to physical addresses; the
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same address is used (as of SH7724 Reference, 10.3.3) */
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if(a >= 0xe5200000 && a < 0xe5204000)
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return a;
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/* First additional on-chip memory area (XRAM) */
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if(a >= 0xe5007000 && a < 0xe5009000)
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return a;
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/* Second on-chip memory area (YRAM) */
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if(a >= 0xe5017000 && a < 0xe5019000)
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return a;
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/* Translate P1 and P2 addresses to ROM and RAM to physical form */
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if(a >= 0x80000000 && a < 0xc0000000)
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return a & 0x1fffffff;
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/* By default: I don't know what this is, let's preserve it */
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return a;
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}
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//---
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// Driver interface
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//---
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/* dma_setup(): Setup the DMA in interrupt or no-interrupt mode.
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The first parameters are as for dma_transfer() and dma_transfer_atomic().
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The last parameter indicates whether interrupts should be used.
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Returns non-zero if the DMA is busy or a configuration error occurs. */
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static int dma_setup(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode,
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int interrupts)
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{
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channel_t *ch = dma_channel(channel);
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if(!ch) return 1;
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/* Safety guard: only start a transfer if there's not one running */
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if(ch->CHCR.DE) return 1;
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/* Disable channel and disable the master DMA switch */
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ch->CHCR.DE = 0;
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DMA.OR.DME = 0;
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/* Set DMA source and target address */
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ch->SAR = dma_translate(src);
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ch->DAR = dma_translate(dst);
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/* Set the number of blocks to be transferred */
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ch->TCR = blocks;
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/* Fill in CHCR. Set RS=0100 (auto-request) and the user-provided
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values for TS (transfer size), DM and SM (address modes) */
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ch->CHCR.lword = 0x00000400;
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ch->CHCR.TS_32 = (size >> 2);
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ch->CHCR.TS_10 = (size & 3);
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ch->CHCR.DM = dst_mode;
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ch->CHCR.SM = src_mode;
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ch->CHCR.IE = !!interrupts;
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/* Prepare DMAOR by enabling the master switch and clearing the
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blocking flags. */
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DMA.OR.DME = 1;
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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/* Block sleep when the transfer involves on-chip memory */
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dma_sleep_blocking[channel] = false;
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if(ch->SAR >= 0xe5007000 && ch->SAR <= 0xe5204000)
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dma_sleep_blocking[channel] = true;
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if(ch->DAR >= 0xe5007000 && ch->DAR <= 0xe5204000)
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dma_sleep_blocking[channel] = true;
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if(ch->SAR >= 0xfe200000 && ch->SAR <= 0xfe3fffff)
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dma_sleep_blocking[channel] = true;
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if(ch->DAR >= 0xfe200000 && ch->DAR <= 0xfe3fffff)
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dma_sleep_blocking[channel] = true;
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return 0;
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}
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bool dma_transfer_async(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode, void *dst,
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dma_address_t dst_mode, gint_call_t callback)
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{
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if(dma_setup(channel, size, blocks, src, src_mode, dst, dst_mode, 1))
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return false;
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dma_callbacks[channel] = callback;
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if(dma_sleep_blocking[channel])
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sleep_block();
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/* Enable channel, starting the DMA transfer. */
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channel_t *ch = dma_channel(channel);
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ch->CHCR.DE = 1;
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return true;
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}
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/* Interrupt handler for all finished DMA transfers */
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static void dma_interrupt_transfer_ended(int channel)
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{
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channel_t *ch = dma_channel(channel);
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ch->CHCR.DE = 0;
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ch->CHCR.TE = 0;
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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if(dma_sleep_blocking[channel])
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sleep_unblock();
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/* Cancel any sleep operation that is synchronized with this interrupt */
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if(dma_wait_ics[channel])
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cpu_csleep_cancel(dma_wait_ics[channel]);
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if(dma_callbacks[channel].function)
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{
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gint_call(dma_callbacks[channel]);
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dma_callbacks[channel] = GINT_CALL_NULL;
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}
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}
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/* dma_transfer_wait(): Wait for a transfer to finish */
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void dma_transfer_wait(int channel)
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{
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if(channel < 0)
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{
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for(int channel = 0; channel < 6; channel++)
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dma_transfer_wait(channel);
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return;
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}
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channel_t *ch = dma_channel(channel);
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if(!ch) return;
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/* Interrupt disabled: spin-wait */
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if(!ch->CHCR.IE)
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{
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while(ch->CHCR.DE && !ch->CHCR.TE) {}
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return;
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}
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/* Initialize an interrupt-cancellable sleep, to ensure synchronization */
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cpu_csleep_t ics;
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cpu_csleep_init(&ics);
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dma_wait_ics[channel] = &ics;
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/* Now the ICS is set; if the interrupt has not occurred yet then the
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handler is guaranteed to cancel the sleep at some point */
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if(ch->CHCR.DE && !ch->CHCR.TE) cpu_csleep(&ics);
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/* Clear the ICS pointer for next time */
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dma_wait_ics[channel] = NULL;
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}
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bool dma_transfer_sync(int channel, dma_size_t size, uint length,
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void const *src, dma_address_t src_mode, void *dst,
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dma_address_t dst_mode)
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{
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if(!dma_transfer_async(channel, size, length, src, src_mode, dst,
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dst_mode, GINT_CALL_NULL)) return false;
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dma_transfer_wait(channel);
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return true;
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}
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/* dma_transfer_atomic(): Perform a data transfer without interruptions */
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void dma_transfer_atomic(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode)
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{
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if(dma_setup(channel, size, blocks, src, src_mode, dst, dst_mode, 0))
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return;
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/* Enable channel, starting the DMA transfer. */
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channel_t *ch = dma_channel(channel);
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ch->CHCR.DE = 1;
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/* Actively wait until the transfer is finished */
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while(!ch->CHCR.TE);
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/* Disable the channel and clear the TE flag. Disable the channel first
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as clearing the TE flag will allow the transfer to restart */
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ch->CHCR.DE = 0;
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ch->CHCR.TE = 0;
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/* Clear the AE and NMIF status flags */
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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}
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/* Deprecated version of dma_transfer_async() that did not have a callback */
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void dma_transfer(int channel, dma_size_t size, uint length, void const *src,
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dma_address_t src_mode, void *dst, dma_address_t dst_mode)
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{
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dma_transfer_async(channel, size, length, src, src_mode, dst, dst_mode,
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GINT_CALL_NULL);
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}
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//---
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// Initialization
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//---
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static void configure(void)
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{
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if(isSH3()) return;
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/* Install the interrupt handler from dma/inth.s */
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int codes[] = { 0x800, 0x820, 0x840, 0x860, 0xb80, 0xba0 };
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extern void inth_dma_te(void);
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for(int i = 0; i < 6; i++)
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{
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intc_handler_function(codes[i],
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GINT_CALL(dma_interrupt_transfer_ended, i));
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/* Disable the channel */
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dma_channel(i)->CHCR.DE = 0;
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}
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/* Install the address error gate */
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extern void inth_dma_ae(void);
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intc_handler(0xbc0, inth_dma_ae, 32);
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/* Set interrupt priority to 3, except 11 for the channels that are
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used by the USB driver */
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intc_priority(INTC_DMA_DEI0, 3);
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intc_priority(INTC_DMA_DEI1, 3);
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intc_priority(INTC_DMA_DEI2, 3);
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intc_priority(INTC_DMA_DEI3, 9);
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intc_priority(INTC_DMA_DEI4, 9);
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intc_priority(INTC_DMA_DEI5, 3);
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intc_priority(INTC_DMA_DADERR, 3);
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/* Clear blocking flags and enable the master switch */
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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DMA.OR.DME = 1;
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}
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static void universal_unbind(void)
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{
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/* Make sure any DMA transfer is finished before leaving the app */
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dma_transfer_wait(-1);
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}
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static bool hpowered(void)
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{
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if(isSH3()) return false;
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return (POWER.MSTPCR0.DMAC0 == 0);
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}
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static void hpoweron(void)
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{
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if(isSH3()) return;
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POWER.MSTPCR0.DMAC0 = 0;
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}
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static void hpoweroff(void)
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{
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if(isSH3()) return;
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POWER.MSTPCR0.DMAC0 = 1;
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}
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//---
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// State and driver metadata
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//---
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static void hsave(dma_state_t *s)
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{
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if(isSH3()) return;
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for(int i = 0; i < 6; i++)
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{
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channel_t *ch = dma_channel(i);
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s->ch[i].SAR = ch->SAR;
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s->ch[i].DAR = ch->DAR;
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s->ch[i].TCR = ch->TCR;
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s->ch[i].CHCR.lword = ch->CHCR.lword;
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}
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s->OR = DMA.OR.word;
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}
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static void hrestore(dma_state_t const *s)
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{
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if(isSH3()) return;
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/* Disable the DMA while editing */
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DMA.OR.DME = 0;
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for(int i = 0; i < 6; i++)
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{
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channel_t *ch = dma_channel(i);
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ch->SAR = s->ch[i].SAR;
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ch->DAR = s->ch[i].DAR;
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ch->TCR = s->ch[i].TCR;
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ch->CHCR.lword = s->ch[i].CHCR.lword;
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}
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DMA.OR.word = s->OR;
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}
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gint_driver_t drv_dma0 = {
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.name = "DMA",
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.configure = configure,
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.funbind = universal_unbind,
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.unbind = universal_unbind,
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.hpowered = hpowered,
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.hpoweron = hpoweron,
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.hpoweroff = hpoweroff,
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.hsave = (void *)hsave,
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.hrestore = (void *)hrestore,
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.state_size = sizeof(dma_state_t),
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};
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GINT_DECLARE_DRIVER(05, drv_dma0);
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