144 lines
3.1 KiB
C
144 lines
3.1 KiB
C
#include <gint/mpu.h>
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#include <gint/mpu/dma.h>
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#include <gint/mpu/power.h>
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#include <gint/mpu/intc.h>
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#include <gint/gint.h>
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#include <gint/dma.h>
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#include <gint/drivers.h>
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#include <gint/clock.h>
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#define DMA SH7305_DMA
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#define INTC SH7305_INTC
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#define POWER SH7305_POWER
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//---
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// Driver interface
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//---
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/* dma_transfer() - Perform a data transfer */
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void dma_transfer(dma_size_t size, uint blocks,
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void *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode)
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{
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/* Safety guard: only start a transfer if there's not one running */
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if(DMA.DMA0.CHCR.DE) return;
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/* Disable DMA0 and disable the master DMA switch */
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DMA.DMA0.CHCR.DE = 0;
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DMA.OR.DME = 0;
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/* Set DMA source and target address */
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DMA.DMA0.SAR = (uint32_t)src & 0x1fffffff;
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DMA.DMA0.DAR = (uint32_t)dst & 0x1fffffff;
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/* Set the number of blocks to be transferred */
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DMA.DMA0.TCR = blocks;
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/* Fill in CHCR. Set RS=0100 (auto-request) and the user-provided
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values for TS (transfer size), DM and SM (address modes) */
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DMA.DMA0.CHCR.lword = 0x00000400;
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DMA.DMA0.CHCR.TS_32 = (size >> 2);
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DMA.DMA0.CHCR.TS_10 = (size & 3);
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DMA.DMA0.CHCR.DM = dst_mode;
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DMA.DMA0.CHCR.SM = src_mode;
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DMA.DMA0.CHCR.IE = 1;
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/* Prepare DMAOR by enabling the master switch and clearing the
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blocking flags. */
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DMA.OR.DME = 1;
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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/* Enable channel 0, starting the DMA transfer. */
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DMA.DMA0.CHCR.DE = 1;
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}
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/* dma_transfer_wait() - Wait for a transfer on channel 0 to finish */
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void dma_transfer_wait(void)
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{
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/* The master switch is cut when the transfer ends */
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while(DMA.OR.DME) sleep();
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}
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//---
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// Initialization
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//---
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static void init(void)
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{
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/* This driver is not implemented on SH3 */
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if(isSH3()) return;
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/* Install the interrupt handler from dma/inth.s */
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extern void inth_dma_dma0(void);
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gint_inthandler(0x800, inth_dma_dma0, 32);
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/* Set interrupt priority to 3 */
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gint_intlevel(16, 3);
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/* Unmask the DMA0 interrupt */
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INTC.MSKCLR->IMR1 = 0x01;
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}
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//---
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// Context system for this driver
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//---
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typedef struct
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{
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uint32_t SAR0, DAR0, TCR0, CHCR0;
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uint16_t OR;
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int clock;
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} GPACKED(4) ctx_t;
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/* One buffer for the system state will go in gint's .bss section */
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GBSS static ctx_t sys_ctx;
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static void ctx_save(void *buf)
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{
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ctx_t *ctx = buf;
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ctx->SAR0 = DMA.DMA0.SAR;
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ctx->DAR0 = DMA.DMA0.DAR;
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ctx->TCR0 = DMA.DMA0.TCR;
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ctx->CHCR0 = DMA.DMA0.CHCR.lword;
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ctx->OR = DMA.OR.word;
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/* Save the supply status of the DMA0 clock */
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ctx->clock = POWER.MSTPCR0.DMAC0;
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}
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static void ctx_restore(void *buf)
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{
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ctx_t *ctx = buf;
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DMA.DMA0.SAR = ctx->SAR0;
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DMA.DMA0.DAR = ctx->DAR0;
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DMA.DMA0.TCR = ctx->TCR0;
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DMA.DMA0.CHCR.lword = ctx->CHCR0;
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DMA.OR.word = ctx->OR;
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/* Restore the supply status of the DMA0 clock */
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POWER.MSTPCR0.DMAC0 = ctx->clock;
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}
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//---
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// Driver structure definition
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//---
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gint_driver_t drv_dma = {
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.name = "DMA",
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.init = init,
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/* Make sure any DMA transfer is finished before leaving the app */
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.unload = dma_transfer_wait,
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.ctx_size = sizeof(ctx_t),
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.sys_ctx = &sys_ctx,
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.ctx_save = ctx_save,
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.ctx_restore = ctx_restore,
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};
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GINT_DECLARE_DRIVER(2, drv_dma);
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