392 lines
11 KiB
C
392 lines
11 KiB
C
//---
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// gint:intc:usb - USB 2.0 Interface
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//---
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#ifndef GINT_MPU_USB
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#define GINT_MPU_USB
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/types.h>
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typedef struct
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{
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word_union(TRE,
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uint16_t :6;
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uint16_t TRENB :1; /* Transaction Counter Enable */
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uint16_t TRCLR :1; /* Transaction Counter Clear */
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uint16_t :8;
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);
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word_union(TRN,
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uint16_t TRCNT :16; /* Transaction Counter */
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);
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} sh7305_usb_pipetr;
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typedef volatile struct
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{
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/* System Configuration Control Register */
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word_union(SYSCFG,
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uint16_t :5;
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uint16_t SCKE :1; /* USB Module Clock Enabled */
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uint16_t :2;
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uint16_t HSE :1; /* High Speed Enable */
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uint16_t DCFM :1; /* Controller Function Select */
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uint16_t DRPD :1; /* D+/D- Line Resistor Control */
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uint16_t DPRPU :1; /* D+ Line Resistor Control */
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uint16_t :3;
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uint16_t USBE :1; /* USB Module Enable */
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);
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/* CPU Bus Wait Setting Register */
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word_union(BUSWAIT,
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uint16_t :8;
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t :1;
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uint16_t _2 :1; /* Unknown role; can be set */
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uint16_t :1;
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uint16_t BWAIT :4; /* Bus Wait */
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);
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/* System Configuration Status Register */
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const word_union(SYSSTS,
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uint16_t :14;
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uint16_t LNST :2; /* Line Status */
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);
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pad(2);
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/* Device State Control Register */
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word_union(DVSTCTR,
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t :2;
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uint16_t _2 :4; /* Unknown role; can be set */
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uint16_t WKUP :1; /* Wakeup Output */
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uint16_t RWUPE :1; /* Wakeup Detection Enable */
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uint16_t USBRT :1; /* USB Reset Output */
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uint16_t RESUME :1; /* Resume Output */
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uint16_t UACT :1; /* USB Bus Enable */
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uint16_t :1;
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uint16_t RHST :3; /* Reset Handshake */
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);
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pad(2);
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/* Test Mode Register */
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word_union(TESTMODE,
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uint16_t :12;
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uint16_t UTST :4; /* Test Mode */
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);
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pad(6);
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/* FIFO Port Registers */
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uint32_t CFIFO; /* DCP FIFO port */
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uint32_t D0FIFO; /* Data 0 FIFO port */
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uint32_t D1FIFO; /* Data 1 FIFO port */
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/* FIFO Port Select and Control Registers */
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word_union(CFIFOSEL,
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uint16_t RCNT :1; /* Read Count Mode */
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uint16_t REW :1; /* Pointer Buffer Rewind */
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uint16_t :2;
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uint16_t MBW :2; /* Access Bits Width */
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uint16_t :1;
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uint16_t BIGEND :1; /* Endiant Control */
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uint16_t :2;
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uint16_t ISEL :1; /* Access Direction When DCP is used */
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uint16_t :1;
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uint16_t CURPIPE:4; /* Port Access Pipe Specification */
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);
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word_union(CFIFOCTR,
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uint16_t BVAL :1; /* Buffer Memory Valid Flags */
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uint16_t BCLR :1; /* CPU Buffer Clear */
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uint16_t FRDY :1; /* FIFO Port Ready */
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uint16_t :1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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pad(4);
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word_union(D0FIFOSEL,
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uint16_t RCNT :1; /* Read Count Mode */
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uint16_t REW :1; /* Pointer Buffer Rewind */
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uint16_t DCLRM :1; /* Auto Buffer Clear Mode */
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uint16_t DREQE :1; /* DMA Transfert Request Enable */
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uint16_t MBW :2; /* Access Bits Width */
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uint16_t :1;
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uint16_t BIGEND :1; /* Endian Control */
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t :3;
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uint16_t CURPIPE:4; /* Port Access Pipe Specification */
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);
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word_union(D0FIFOCTR,
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uint16_t BVAL :1; /* Buffer Memory Valid Flags */
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uint16_t BCLR :1; /* CPU Buffer Clear */
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uint16_t FRDY :1; /* FIFO Port Ready */
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uint16_t :1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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word_union(D1FIFOSEL,
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uint16_t RCNT :1; /* Read Count Mode */
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uint16_t REW :1; /* Pointer Buffer Rewind */
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uint16_t DCLRM :1; /* Auto Buffer Clear Mode */
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uint16_t DREQE :1; /* DMA Transfert Request Enable */
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uint16_t MBW :2; /* Access Bits Width */
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uint16_t :1;
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uint16_t BIGEND :1; /* Endian Control */
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t :3;
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uint16_t CURPIPE:4; /* Port Access Pipe Specification */
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);
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word_union(D1FIFOCTR,
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uint16_t BVAL :1; /* Buffer Memory Valid Flags */
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uint16_t BCLR :1; /* CPU Buffer Clear */
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uint16_t FRDY :1; /* FIFO Port Ready */
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uint16_t :1;
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uint16_t DTLN :12; /* Receive Data Length */
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);
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/* Interrupts Enable Registers */
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word_union(INTENB0,
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uint16_t VBSE :1; /* VBUS */
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uint16_t RSME :1; /* Resume */
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uint16_t SOFE :1; /* Frame Number Update */
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uint16_t DVSE :1; /* Device State Transition */
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uint16_t CTRE :1; /* Control Transfer Stage Transition */
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uint16_t BEMPE :1; /* Buffer Empty */
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uint16_t NRDYE :1; /* Buffer Not Ready */
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uint16_t BRDYE :1; /* Buffer Ready */
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uint16_t :8;
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);
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word_union(INTENB1,
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t BCHGE :1; /* Bus Change */
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uint16_t :1;
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uint16_t DTCHE :1; /* Disconnection Detection */
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uint16_t ATTCHE :1; /* Connection Detection */
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uint16_t :4;
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uint16_t EOFERRE:1; /* EOF Error Detection */
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uint16_t SIGNE :1; /* Setup Transaction Error */
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uint16_t SACKE :1; /* Setup Transaction Normal Response */
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uint16_t :4;
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);
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pad(2);
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/* BRDY Interrupt Enable Register */
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uint16_t BRDYENB;
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/* NRDY Interrupt Enable Register */
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uint16_t NRDYENB;
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/* BEMP Interrupt Enable Register */
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uint16_t BEMPENB;
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/* SOF Control Register */
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word_union(SOFCFG,
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uint16_t :7;
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uint16_t TRNENSEL :1; /* Transaction-Enabled Time Select */
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uint16_t :1;
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uint16_t BRDYM :1; /* BRDY Status Clear Timing */
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uint16_t enable :1; /* SHOULD BE SET TO 1 MANUALLY */
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uint16_t :1;
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t _2 :1; /* Unknown role; can be set */
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uint16_t :2;
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);
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pad(2);
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/* Interrupt Status Registers */
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word_union(INTSTS0,
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uint16_t VBINT :1; /* VBUS */
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uint16_t RESM :1; /* Resume */
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uint16_t SOFR :1; /* Frame Number Refresh */
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uint16_t DVST :1; /* Device State Transition */
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uint16_t CTRT :1; /* Control Transfer Stage Transition */
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uint16_t BEMP :1; /* Buffer Empty */
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uint16_t NRDY :1; /* Buffer Not Ready */
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uint16_t BRDY :1; /* Buffer Ready */
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uint16_t VBSTS :1; /* VBUS Input Status */
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uint16_t DVSQ :3; /* Device state */
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uint16_t VALID :1; /* USB Request Reception */
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uint16_t CTSQ :3; /* Control Transfer Stage */
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);
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word_union(INTSTS1,
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uint16_t _1 :1; /* Unknown role */
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uint16_t BCHG :1; /* Bus Change */
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uint16_t :1;
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uint16_t DTCH :1; /* Disconnection Detection */
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uint16_t ATTCH :1; /* Connection Detection */
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uint16_t :4;
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uint16_t EOFERR :1; /* EOF Error Detection */
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uint16_t SIGN :1; /* Setup Transaction Error */
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uint16_t SACK :1; /* Setup Transaction Normal Response */
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uint16_t :4;
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);
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pad(2);
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/* BRDY Interrupt Status Register */
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uint16_t BRDYSTS;
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/* NRDY Interrupt Status Register */
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uint16_t NRDYSTS;
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/* BEMP Interrupt Status Register */
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uint16_t BEMPSTS;
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/* Frame Number Registers */
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word_union(FRMNUM,
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uint16_t OVRN :1; /* Overrun/Underrun Detection Status */
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uint16_t CRCE :1; /* Receive Data Error */
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uint16_t const :3;
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uint16_t FRNM :11; /* Frame Number */
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);
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word_union(UFRMNUM,
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uint16_t :13;
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uint16_t UFRNM :3; /* uFrame */
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);
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/* USB Address Register */
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word_union(USBADDR,
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uint16_t :9;
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uint16_t const USBADDR :7; /* USB Address */
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);
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pad(2);
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/* USB Request Type Register */
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word_union(USBREQ,
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uint16_t BREQUEST :8; /* USB request data value */
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uint16_t BMREQUEST :8; /* USB request type value */
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);
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/* USB Request Value Register */
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word_union(USBVAL,
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uint16_t WVALUE :16; /* USB request wValue value */
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);
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/* USB Request Index Register */
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word_union(USBINDX,
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uint16_t WINDEX :16; /* USB USB request wIndex value */
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);
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/* USB Request Length Register */
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word_union(USBLENG,
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uint16_t WLENGTH :16; /* USB USB request wLength value */
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);
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/* DCP Configuration Register */
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word_union(DCPCFG,
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uint16_t :7;
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uint16_t _1 :1; /* Unknown role; can be set */
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uint16_t _2 :1; /* Unknown role; can be set */
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uint16_t :2;
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uint16_t DIR :1; /* Transfer Direction */
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uint16_t :4;
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);
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/* DCP Maximum Packet Size Register */
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word_union(DCPMAXP,
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uint16_t DEVSEL :4; /* Device Select */
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uint16_t :5;
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uint16_t MXPS :7; /* Maximum Packet Size */
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);
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/* DCP Control Register */
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word_union(DCPCTR,
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uint16_t BSTS :1; /* Buffer Status */
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uint16_t SUREQ :1; /* SETUP Token Transmission */
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uint16_t CSCLR :1; /* C-SPLIT Status Clear */
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uint16_t CSSTS :1; /* C-SPLIT Status */
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uint16_t SUREQCLR :1; /* SUREQ Bit Clear */
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uint16_t :2;
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uint16_t SQCLR :1; /* Toggle Bit Clear */
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uint16_t SQSET :1; /* Toggle Bit Set */
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uint16_t SQMON :1; /* Sequence Toggle Bit Monitor */
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uint16_t PBUSY :1; /* Pipe Busy */
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uint16_t PINGE :1; /* PING Token Issue Enable */
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uint16_t :1;
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uint16_t CCPL :1; /* Control Transfer End Enable */
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uint16_t PID :2; /* Response PID */
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);
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pad(2);
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/* Pipe Window Select Register */
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word_union(PIPESEL,
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uint16_t :12;
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uint16_t PIPESEL :4; /* Pipe Window Select */
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);
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pad(2);
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/* Pipe Configuration Register */
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word_union(PIPECFG,
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uint16_t TYPE :2; /* Transfer Type */
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uint16_t :3;
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uint16_t BFRE :1; /* BRDY Interrupt Operation Specification */
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uint16_t DBLB :1; /* Double Buffer Mode */
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uint16_t CNTMD :1; /* Continuous Transfer Mode */
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uint16_t SHTNAK :1; /* Pipe Disabled at End of Transfer */
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uint16_t :2;
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uint16_t DIR :1; /* Transfer Direction */
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uint16_t EPNUM :4; /* Endpoint Number */
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);
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/* Pipe Buffer Setting Register */
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word_union(PIPEBUF,
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uint16_t :1;
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uint16_t BUFSIZE:5; /* Buffer Size */
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uint16_t :2;
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uint16_t BUFNMB :8; /* Buffer Number */
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);
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/* Pipe Maximum Packet Size Register */
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word_union(PIPEMAXP,
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uint16_t DEVSEL :4; /* Device Select */
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uint16_t :1;
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uint16_t MXPS :11; /* Maximum Packet Size */
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);
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/* Pipe Timing Control Register */
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word_union(PIPEPERI,
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uint16_t :3;
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uint16_t IFIS :1; /* Isochronous IN Buffer Flush */
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uint16_t :9;
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uint16_t IITV :3; /* Interval Error Detection Interval */
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);
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/* PIPEn Control Registers */
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word_union(PIPECTR[9],
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uint16_t BSTS :1; /* Buffer Status */
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uint16_t INBUFM :1; /* IN Buffer Monitor (PIPE1..5) */
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uint16_t CSCLR :1; /* C-SPLIT Status Clear Bit */
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uint16_t CSSTS :1; /* CSSTS Status Bit */
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uint16_t :1;
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uint16_t ATREPM :1; /* Auto Response Mode (PIPE1..5) */
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uint16_t ACLRM :1; /* Auto Buffer Clear Mode */
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uint16_t SQCLR :1; /* Toggle Bit Clear */
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uint16_t SQSET :1; /* Toggle Bit Set */
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uint16_t SQMON :1; /* Toggle Bit Confirmation */
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uint16_t PBUSY :1; /* Pipe Busy */
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uint16_t :3;
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uint16_t PID :2; /* Response PID */
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);
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pad(14);
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/* Transaction Counter Registers (PIPE1..PIPE5 only) */
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sh7305_usb_pipetr PIPETR[5];
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pad(0x1e);
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uint16_t REG_C2;
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pad(12);
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word_union(DEVADD[11],
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uint16_t :1;
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uint16_t UPPHUB :4; /* Address of target's hub */
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uint16_t HUBPORT:3; /* Hub port where target connects */
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uint16_t USBSPD :2; /* Transfer speed / Target present */
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uint16_t :6;
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);
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} GPACKED(4) sh7305_usb_t;
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typedef volatile word_union(sh7305_usb_uponcr_t,
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uint16_t :5;
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uint16_t UPON :2; /* USB Power ON */
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uint16_t :9;
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);
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#define SH7305_USB (*(sh7305_usb_t *)0xa4d80000)
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#define SH7305_USB_UPONCR (*(sh7305_usb_uponcr_t *)0xa40501d4)
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_USB */
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