549 lines
16 KiB
C
549 lines
16 KiB
C
//---
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// gint:cpg:overclock - Clock speed control
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//
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// Most of the data in this file has been reused from Sentaro21's Ftune and
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// Ptune utilities, which have long been the standard for overclocking CASIO
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// calculators.
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// See: http://pm.matrix.jp/ftune2e.html
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//
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// SlyVTT also contributed early testing on both the fx-CG 10/20 and fx-CG 50.
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//---
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#include <gint/clock.h>
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#include <gint/gint.h>
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#include <gint/hardware.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/bsc.h>
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#include <gint/mpu/wdt.h>
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/*
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define SH7705_CPG SH7705_CPG
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#define SH7705_BSC SH7705_BSC
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#define SH7705_WDT SH7705_WDT
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*/
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//---
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// Low-level clock speed access
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//---
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#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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//---
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// Predefined clock speeds
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//---
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// for SH4 based calculators
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#define SH4_PLL_32x 0b011111
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#define SH4_PLL_26x 0b011001
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#define SH4_PLL_16x 0b001111
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#define SH4_DIV_2 0
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#define SH4_DIV_4 1
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#define SH4_DIV_8 2
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#define SH4_DIV_16 3
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#define SH4_DIV_32 4
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// for SH3 based calculators
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#define SH3_PLL_1x 0 //0b0000 // x1
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#define SH3_PLL_2x 1 //0b0001 // x2
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#define SH3_PLL_3x 2 //0b0010 // x3
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#define SH3_PLL_4x 3 //0b0011 // x4
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#define SH3_DIV_1 0 //0b0000 // 1/1
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#define SH3_DIV_2 1 //0b0001 // 1/2
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#define SH3_DIV_3 2 //0b0010 // 1/3
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#define SH3_DIV_4 3 //0b0011 // 1/4
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static struct cpg_overclock_setting save_parameters_at_start = {0};
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static bool is_initial_state_saved = false;
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(isSH3())
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{
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s->FLLFRQ = 0xFFFFFFF; // not used for SH3 MPUs
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s->FRQCR = (uint32_t) SH7705_CPG.FRQCR.word;
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s->CS0BCR = SH7705_BSC.CS0BCR.lword;
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s->CS0WCR = SH7705_BSC.CS0WCR.lword;
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s->CS2BCR = SH7705_BSC.CS2BCR.lword;
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s->CS2WCR = SH7705_BSC.CS2WCR.lword;
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s->CS3BCR = SH7705_BSC.CS3BCR.lword;
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s->CS3WCR = SH7705_BSC.CS3WCR.lword;
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s->CS5aBCR = SH7705_BSC.CS5ABCR.lword;
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s->CS5aWCR = SH7705_BSC.CS5AWCR.lword;
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}
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if(isSH4())
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{
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s->FLLFRQ = SH7305_CPG.FLLFRQ.lword;
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s->FRQCR = SH7305_CPG.FRQCR.lword;
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s->CS0BCR = SH7305_BSC.CS0BCR.lword;
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s->CS0WCR = SH7305_BSC.CS0WCR.lword;
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s->CS2BCR = SH7305_BSC.CS2BCR.lword;
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s->CS2WCR = SH7305_BSC.CS2WCR.lword;
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s->CS3BCR = SH7305_BSC.CS3BCR.lword;
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s->CS3WCR = SH7305_BSC.CS3WCR.lword;
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s->CS5aBCR = SH7305_BSC.CS5ABCR.lword;
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s->CS5aWCR = SH7305_BSC.CS5AWCR.lword;
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}
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return;
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}
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void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(isSH3())
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{
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SH7705_WDT.WTCNT.WRITE = 0;
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SH7705_WDT.WTCSR.WRITE = 0x65;
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SH7705_CPG.FRQCR.word = (uint16_t) (0x1000 | ((uint16_t) s->FRQCR));
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SH7705_BSC.CS0BCR.lword = s->CS0BCR;
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SH7705_BSC.CS0WCR.lword = s->CS0WCR;
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SH7705_BSC.CS2BCR.lword = s->CS2BCR;
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SH7705_BSC.CS2WCR.lword = s->CS2WCR;
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SH7705_BSC.CS3BCR.lword = s->CS3BCR;
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SH7705_BSC.CS3WCR.lword = s->CS3WCR;
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SH7705_BSC.CS5ABCR.lword = s->CS5aBCR;
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SH7705_BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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if(isSH4())
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{
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SH7305_BSC.CS0WCR.WR = 11; /* 18 cycles */
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SH7305_CPG.FLLFRQ.lword = s->FLLFRQ;
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SH7305_CPG.FRQCR.lword = s->FRQCR;
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SH7305_CPG.FRQCR.KICK = 1;
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while(SH7305_CPG.LSTATS != 0) {}
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SH7305_BSC.CS0BCR.lword = s->CS0BCR;
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SH7305_BSC.CS0WCR.lword = s->CS0WCR;
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SH7305_BSC.CS2BCR.lword = s->CS2BCR;
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SH7305_BSC.CS2WCR.lword = s->CS2WCR;
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SH7305_BSC.CS3BCR.lword = s->CS3BCR;
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SH7305_BSC.CS3WCR.lword = s->CS3WCR;
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if(SH7305_BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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SH7305_BSC.CS5ABCR.lword = s->CS5aBCR;
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SH7305_BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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return;
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}
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void clock_save_state(void)
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{
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cpg_get_overclock_setting( &save_parameters_at_start );
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is_initial_state_saved = true;
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}
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void clock_restore_state(void)
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{
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if(is_initial_state_saved==true)
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cpg_set_overclock_setting( &save_parameters_at_start );
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}
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/*settings for the fxcg50 / G90+E*/
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static struct cpg_overclock_setting settings_fxcg50[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F011112,
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.CS0BCR = 0x36DA0400,
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.CS2BCR = 0x36DA3400,
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.CS3BCR = 0x36DB4400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000340,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000240,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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};
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/*settings for the prizm fxcg10/20*/
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static struct cpg_overclock_setting settings_prizm[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F102203,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000001C0,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_16<<12)+(SH4_DIV_16<<8)+SH4_DIV_32,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x000100C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_32,
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.CS0BCR = 0x24900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000201C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_32,
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.CS0BCR = 0x44900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x00040340,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (SH4_PLL_26x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
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.CS0BCR = 0x34900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000402C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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};
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/*settings for the fx9860G SH3 based*/
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static struct cpg_overclock_setting settings_fx9860g_sh3[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = 0x1001,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_2x<<8)+(SH3_DIV_1<<4)+SH3_DIV_2,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_3x<<8)+(SH3_DIV_1<<4)+SH3_DIV_3,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0xFFFFFFFF, // not used for SH3 MPUs
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.FRQCR = (SH3_PLL_4x<<8)+(SH3_DIV_1<<4)+SH3_DIV_4,
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.CS0BCR = 0x02480400,
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.CS2BCR = 0x02483400,
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.CS3BCR = 0x36DB0600,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000000C0,
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.CS2WCR = 0x000100C0,
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.CS3WCR = 0x00000500,
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.CS5aWCR = 0x00000D41 },
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};
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/*settings for the fx9860GII*/
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static struct cpg_overclock_setting settings_fx9860g_sh4[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = 0x0F202203,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000005C0,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000001C0,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x24920200,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000001C0,
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.CS2WCR = 0x00020140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00000D41 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004384,
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.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_4<<8)+SH4_DIV_16,
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.CS0BCR = 0x14900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x224A0200,
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.CS0WCR = 0x000003C0,
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|
.CS2WCR = 0x000302C0,
|
|
.CS3WCR = 0x000024D0,
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|
.CS5aWCR = 0x00000D41 },
|
|
};
|
|
|
|
/*settings for the fx9860GII-2 / G35+EII*/
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|
static struct cpg_overclock_setting settings_g35pe2[5] = {
|
|
/* CLOCK_SPEED_F1 */
|
|
{ .FLLFRQ = 0x00004384,
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|
.FRQCR = 0x0F202203,
|
|
.CS0BCR = 0x24920400,
|
|
.CS2BCR = 0x24923400,
|
|
.CS3BCR = 0x24924400,
|
|
.CS5aBCR = 0x224A0200,
|
|
.CS0WCR = 0x000005C0,
|
|
.CS2WCR = 0x00000140,
|
|
.CS3WCR = 0x000024D0,
|
|
.CS5aWCR = 0x00000D41 },
|
|
/* CLOCK_SPEED_F2 */
|
|
{ .FLLFRQ = 0x00004384,
|
|
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
|
.CS0BCR = 0x24920400,
|
|
.CS2BCR = 0x24923400,
|
|
.CS3BCR = 0x24924400,
|
|
.CS5aBCR = 0x224A0200,
|
|
.CS0WCR = 0x000001C0,
|
|
.CS2WCR = 0x00000140,
|
|
.CS3WCR = 0x000024D0,
|
|
.CS5aWCR = 0x00000D41 },
|
|
/* CLOCK_SPEED_F3 */
|
|
{ .FLLFRQ = 0x00004384,
|
|
.FRQCR = (SH4_PLL_16x<<24)+(SH4_DIV_8<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
|
.CS0BCR = 0x04900400,
|
|
.CS2BCR = 0x04903400,
|
|
.CS3BCR = 0x24924400,
|
|
.CS5aBCR = 0x224A0200,
|
|
.CS0WCR = 0x00000140,
|
|
.CS2WCR = 0x00000140,
|
|
.CS3WCR = 0x000024D0,
|
|
.CS5aWCR = 0x00000D41 },
|
|
/* CLOCK_SPEED_F4 */
|
|
{ .FLLFRQ = 0x00004384,
|
|
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
|
.CS0BCR = 0x04900400,
|
|
.CS2BCR = 0x04903400,
|
|
.CS3BCR = 0x24924400,
|
|
.CS5aBCR = 0x224A0200,
|
|
.CS0WCR = 0x000001C0,
|
|
.CS2WCR = 0x00020140,
|
|
.CS3WCR = 0x000024D0,
|
|
.CS5aWCR = 0x00031340 },
|
|
/* CLOCK_SPEED_F5 */
|
|
{ .FLLFRQ = 0x00004384,
|
|
.FRQCR = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
|
|
.CS0BCR = 0x14900400,
|
|
.CS2BCR = 0x04903400,
|
|
.CS3BCR = 0x24924400,
|
|
.CS5aBCR = 0x224A0200,
|
|
.CS0WCR = 0x000001C0,
|
|
.CS2WCR = 0x00020140,
|
|
.CS3WCR = 0x000024D0,
|
|
.CS5aWCR = 0x00031340 },
|
|
};
|
|
|
|
static struct cpg_overclock_setting *get_settings(void)
|
|
{
|
|
if(gint[HWCALC] == HWCALC_FXCG50)
|
|
return settings_fxcg50;
|
|
if(gint[HWCALC] == HWCALC_PRIZM)
|
|
return settings_prizm;
|
|
if(gint[HWCALC] == HWCALC_G35PE2)
|
|
return settings_g35pe2;
|
|
if(gint[HWCALC] == HWCALC_FX9860G_SH4)
|
|
return settings_fx9860g_sh4;
|
|
if(gint[HWCALC] == HWCALC_FX9860G_SH3)
|
|
return settings_fx9860g_sh3;
|
|
return NULL;
|
|
}
|
|
|
|
int clock_get_speed(void)
|
|
{
|
|
struct cpg_overclock_setting *settings = get_settings();
|
|
if(!settings)
|
|
return CLOCK_ERROR;
|
|
|
|
if(isSH3())
|
|
{
|
|
for(int i = 0; i < 5; i++) {
|
|
struct cpg_overclock_setting *s = &settings[i];
|
|
|
|
if(SH7705_CPG.FRQCR.word == (uint16_t) (s->FRQCR | 0x1000) // FRQCR is a uint16_t for SH3
|
|
&& SH7705_BSC.CS0BCR.lword == s->CS0BCR
|
|
&& SH7705_BSC.CS2BCR.lword == s->CS2BCR
|
|
&& SH7705_BSC.CS3BCR.lword == s->CS3BCR
|
|
&& SH7705_BSC.CS5ABCR.lword == s->CS5aBCR
|
|
&& SH7705_BSC.CS0WCR.lword == s->CS0WCR
|
|
&& SH7705_BSC.CS2WCR.lword == s->CS2WCR
|
|
&& SH7705_BSC.CS3WCR.lword == s->CS3WCR
|
|
&& SH7705_BSC.CS5AWCR.lword == s->CS5aWCR)
|
|
return CLOCK_SPEED_F1 + i;
|
|
}
|
|
}
|
|
|
|
if(isSH4())
|
|
{
|
|
for(int i = 0; i < 5; i++) {
|
|
struct cpg_overclock_setting *s = &settings[i];
|
|
|
|
if(SH7305_CPG.FLLFRQ.lword == s->FLLFRQ
|
|
&& SH7305_CPG.FRQCR.lword == s->FRQCR // FRQCR is a uint32_t for SH4
|
|
&& SH7305_BSC.CS0BCR.lword == s->CS0BCR
|
|
&& SH7305_BSC.CS2BCR.lword == s->CS2BCR
|
|
&& SH7305_BSC.CS3BCR.lword == s->CS3BCR
|
|
&& SH7305_BSC.CS5ABCR.lword == s->CS5aBCR
|
|
&& SH7305_BSC.CS0WCR.lword == s->CS0WCR
|
|
&& SH7305_BSC.CS2WCR.lword == s->CS2WCR
|
|
&& SH7305_BSC.CS3WCR.lword == s->CS3WCR
|
|
&& SH7305_BSC.CS5AWCR.lword == s->CS5aWCR)
|
|
return CLOCK_SPEED_F1 + i;
|
|
}
|
|
}
|
|
|
|
clock_save_state();
|
|
return CLOCK_SPEED_UNKNOWN;
|
|
}
|
|
|
|
void clock_set_speed(int level)
|
|
{
|
|
if(level < CLOCK_SPEED_F1 || level > CLOCK_SPEED_F5)
|
|
return;
|
|
if(clock_get_speed() == level)
|
|
return;
|
|
|
|
struct cpg_overclock_setting *settings = get_settings();
|
|
if(!settings)
|
|
return;
|
|
|
|
struct cpg_overclock_setting *s = &settings[level - CLOCK_SPEED_F1];
|
|
uint32_t old_Pphi = clock_freq()->Pphi_f;
|
|
|
|
/* Wait for asynchronous tasks to complete */
|
|
gint_world_sync();
|
|
|
|
/* Disable interrupts during the change */
|
|
cpu_atomic_start();
|
|
|
|
/* Set the clock settings */
|
|
cpg_set_overclock_setting(s);
|
|
|
|
/* Determine the change in frequency for Pϕ and recompute CPG data */
|
|
cpg_compute_freq();
|
|
uint32_t new_Pphi = clock_freq()->Pphi_f;
|
|
|
|
/* Update timers' TCNT and TCOR to match the new clock speed */
|
|
void timer_rescale(uint32_t old_Pphi, uint32_t new_Pphi);
|
|
timer_rescale(old_Pphi, new_Pphi);
|
|
|
|
cpu_atomic_end();
|
|
} |