98 lines
2.6 KiB
C
98 lines
2.6 KiB
C
//---
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// gint:mpu:spu - Sound Processing Unit and its DSPs
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//---
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#ifndef GINT_MPU_SPU
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#define GINT_MPU_SPU
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#include <gint/defs/types.h>
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typedef volatile struct
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{
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uint32_t PBANKC0; /* Program Bank Control 0 */
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uint32_t PBANKC1; /* Program Bank Control 1 */
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pad(0x8);
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uint32_t XBANKC0; /* X Bank Control 0 */
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uint32_t XBANKC1; /* X Bank Control 1 */
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pad(0x10);
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lword_union(SPUSRST, /* SPU Software Reset */
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uint32_t :24;
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uint32_t DB3 :1; /* DMABUF 3 */
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uint32_t DB2 :1; /* DMABUF 2 */
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uint32_t DB1 :1; /* DMABUF 1 */
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uint32_t DB0 :1; /* DMABUF 0 */
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uint32_t :3;
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uint32_t RST :1; /* Reset */
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);
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uint32_t const SPUADR; /* SPU address */
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uint32_t const ENDIAN; /* SuperHyway endian */
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pad(0x10);
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uint32_t GCOM[8]; /* Global Common */
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pad(0x20);
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uint32_t const DMABUF[4]; /* Inter-DSP Communication Buffer */
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} GPACKED(4) spu_t;
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typedef volatile struct
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{
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uint32_t SBAR; /* Source base address */
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uint32_t SAR; /* Source address */
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uint32_t DBAR; /* Destination base address */
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uint32_t DAR; /* Destination address */
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uint32_t TCR; /* Transfer count */
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uint32_t SHPRI; /* SHway priority */
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uint32_t CHCR; /* Channel control */
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pad(0x4);
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} GPACKED(4) spu_dsp_dma_t;
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typedef volatile struct {
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uint32_t LSA; /* Loop start address */
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uint32_t LEA; /* Loop end address */
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pad(0x8);
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} GPACKED(4) spu_dsp_loop_t;
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typedef volatile struct
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{
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uint32_t DSPRST; /* DSP full reset */
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uint32_t DSPCORERST; /* DSP core reset */
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uint32_t const DSPHOLD; /* DSP hold */
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uint32_t DSPRESTART; /* DSP restart */
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pad(0x8);
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uint32_t IEMASKC; /* CPU interrupt source mask */
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uint32_t IMASKC; /* CPU interrupt signal mask */
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uint32_t IEVENTC; /* CPU interrupt source */
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uint32_t IEMASKD; /* DSP interrupt source mask */
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uint32_t IMASKD; /* DSP interrupt signal mask */
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uint32_t IESETD; /* DSP interrupt set */
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uint32_t IECLRD; /* DSP interrupt clear */
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uint32_t OR; /* DMAC operation */
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uint32_t COM[8]; /* CPU-DSP communication */
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uint32_t BTADRU; /* Bus-through address high */
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uint32_t BTADRL; /* Bus-through address low */
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uint32_t WDATU; /* Bus-through write data high */
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uint32_t WDATL; /* Bus-through write data low */
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uint32_t RDATU; /* Bus-through read data high */
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uint32_t RDATL; /* Bus-through read data low */
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uint32_t BTCTRL; /* Bus-through mode control */
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uint32_t SPUSTS; /* SPU status */
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pad(0x88);
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spu_dsp_dma_t DMA[3];
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pad(0x20);
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spu_dsp_loop_t LP[3];
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} GPACKED(4) spu_dsp_t;
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#define SH7305_SPU (*(spu_t *)0xfe2ffc00)
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#define SH7305_DSP0 (*(spu_dsp_t *)0xfe2ffd00)
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#define SH7305_DSP1 (*(spu_dsp_t *)0xfe3ffd00)
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#endif /* GINT_MPU_SPU */
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