155 lines
3.7 KiB
ArmAsm
155 lines
3.7 KiB
ArmAsm
/*
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** gint:core:inth - Interrupt handlers
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** This file only contains the entry points because the gates are managed
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** by device drivers. Each driver will supply its own interrupt handler
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** blocks depending on its configuration.
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*/
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.global _gint_inth_7305
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#ifdef FX9860G
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.global _gint_inth_7705
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#endif
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.section .gint.blocks, "ax"
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.align 4
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/* Interrupt handlers
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The .gint.blocks section consists of blocks of 32 bytes intended for mapping
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into the VBR space (exception, TLB miss, and interrupt handlers). Each event
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gate is linearly associated with a block number:
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block_id = (event_code - 0x380) / 0x20
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This file provides entry points; drivers may provide their own interrupt
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handlers, and store them in the .gint.blocks section for consistency. They
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should be aware of the consequences of reordering the blocks into the VBR
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space:
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- It is possible to map MPU-specific blocks at runtime, to avoid checking
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the MPU each time an interrupt is handled;
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- However, the blocks can only rely on relative displacements or cross-
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references if their relative order is known and heeded for. A good example
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of this is the timer driver. Please be careful. */
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/* SH7305-TYPE DEBUG INTERRUPT HANDLER - 26 BYTES */
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#if 0
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_gint_inth_7305:
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mov.l 1f, r0
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mov.l @r0, r4
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sts.l pr, @-r15
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mov.l 2f, r0
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jsr @r0
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nop
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lds.l @r15+, pr
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rte
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nop
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.zero 6
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2: .long _debug
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1: .long 0xff000028
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#endif
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/* SH7305-TYPE INTERRUPT HANDLER ENTRY - 40 BYTES */
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_gint_inth_7305:
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/* Save caller-saved registers which might currently be in use by the
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interrupted function, as we don't know what the callback will do */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT register */
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mov.l 1f, r0
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mov.l @r0, r0
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/* Interrupt codes start at 0x400 */
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mov #4, r1
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shll8 r1
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sub r1, r0
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/* Add the distance to the first entry and jump as a subroutine */
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add #40, r0
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bsrf r0
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nop
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/* Restore caller-saved registers */
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 24
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1: .long 0xff000028
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#ifdef FX9860G
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/* SH7705-TYPE INTERRUT HANDLER ENTRY - 52 BYTES */
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_gint_inth_7705:
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/* Save caller-saved registers as before */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT2 register */
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mov.l 1f, r0
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mov.l @r0, r0 /* r0 = old_code */
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/* Translate the event code to SH4 format */
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mov.l 2f, r2
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mov #-5, r3
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shld r3, r0 /* r0 = old_code >> 5 */
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add #-32, r0 /* r0 = (old_code - 0x400) >> 5 */
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mov.b @(r0, r2), r0 /* r0 = (new_code - 0x400) >> 5 */
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mov #5, r3
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shld r3, r0 /* r0 = new_code - 0x400 */
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/* Add the distance between nop and the first entry, and jump */
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add #32, r0
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bsrf r0
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nop
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/* Restore saved registers */
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lds.l @r15+, mach
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lds.l @r15+, macl
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 12
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1: .long 0xa4000000 /* INTEVT2 register */
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2: .long _inth_remap
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.section .gint.data
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.align 4
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/* EVENT CODE TRANSLATION TABLE - 96 BYTES */
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_inth_remap:
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.byte 0x00, 0x01, 0x02, 0xfe, 0x34, 0x35, 0x36, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f
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.byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x20, 0x21, 0x22, 0x23, 0x28, 0x28, 0xff, 0x28
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.byte 0x48, 0x48, 0xff, 0x48, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0x31, 0x32, 0x33, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x2d, 0x2d, 0xff, 0xff, 0x2d, 0x2d, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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#endif
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