164 lines
3.2 KiB
C
164 lines
3.2 KiB
C
//---
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// gint:mpu:mmu - Memory Management Unit
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//
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// The MMU mainly exposes the contents of the TLB for us to inspect.
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// Functions to manipulate these are exposed by <gint/mmu.h>.
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//---
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#ifndef GINT_MPU_MMU
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#define GINT_MPU_MMU
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 TLB. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 3: "Memory Management Unit (MMU)"
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//---
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/* tlb_addr_t - address part of a TLB entry */
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typedef struct
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{
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uint VPN :22;
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uint :1;
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uint V :1;
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uint ASID :8;
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} GPACKED(4) tlb_addr_t;
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/* tlb_data_t - data part of a TLB entry */
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typedef struct
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{
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uint :3;
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uint PPN :19;
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uint :1;
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uint V :1;
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uint :1;
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uint PR :2;
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uint SZ :1;
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uint C :1;
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uint D :1;
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uint SH :1;
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uint :1;
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} GPACKED(4) tlb_data_t;
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//---
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// SH7305 TLB. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 7: "Memory Management Unit (MMU)"
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//---
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/* utlb_addr_t - address part of a UTLB entry */
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typedef struct
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{
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uint VPN :22;
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uint D :1;
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uint V :1;
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uint ASID :8;
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} GPACKED(4) utlb_addr_t;
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/* utlb_data_t - data part of a UTLB entry */
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typedef struct
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{
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uint :3;
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uint PPN :19;
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uint :1;
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uint V :1;
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uint SZ1 :1;
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uint PR :2;
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uint SZ2 :1;
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uint C :1;
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uint D :1;
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uint SH :1;
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uint WT :1;
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} GPACKED(4) utlb_data_t;
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typedef volatile struct
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{
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lword_union(PTEH,
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uint32_t VPN :22; /* Virtual Page Number */
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uint32_t :2;
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uint32_t ASID :8; /* Address Space Identifier */
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);
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lword_union(PTEL,
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uint32_t :3;
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uint32_t PPN :19; /* Phusical Page Number */
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uint32_t :1;
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uint32_t V :1; /* Valid */
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uint32_t SZ1 :1; /* Size (bit 1) */
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uint32_t PR :2; /* Protection */
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uint32_t SZ0 :1; /* Size (bit 0) */
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uint32_t C :1; /* Cacheable */
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uint32_t D :1; /* Dirty */
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uint32_t SH :1; /* Shared */
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uint32_t WT :1; /* Write-through */
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);
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uint32_t TTB;
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uint32_t TEA;
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lword_union(MMUCR,
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uint32_t LRUI :6; /* Least-Recently Used ITLB */
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uint32_t :2;
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uint32_t URB :6; /* UTLB Replace Boundary */
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uint32_t :2;
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uint32_t URC :6; /* UTLB Replace Counter */
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uint32_t SQMD :1; /* Store Queue Mode */
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uint32_t SV :1; /* Single Virtual Memory Mode */
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uint32_t ME :1; /* TLB Extended Mode */
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uint32_t :4;
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uint32_t TI :1; /* TLB Invalidate */
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uint32_t :1;
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uint32_t AT :1; /* Address Translation */
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);
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pad(0x20);
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lword_union(PTEA,
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uint32_t :18;
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uint32_t EPR :6;
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uint32_t ESZ :4;
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uint32_t :4;
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);
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pad(0x38);
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lword_union(PASCR,
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uint32_t :24;
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uint32_t UBC :1; /* Control register area */
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uint32_t UB6 :1; /* Area 6 */
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uint32_t UB5 :1; /* Area 5 */
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uint32_t UB4 :1; /* Area 4 */
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uint32_t UB3 :1; /* Area 3 */
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uint32_t UB2 :1; /* Area 2 */
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uint32_t UB1 :1; /* Area 1 */
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uint32_t UB0 :1; /* Area 0 */
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);
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pad(4);
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lword_union(IRMCR,
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uint32_t :27;
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uint32_t R2 :1; /* Re-fetch after Register 2 change */
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uint32_t R1 :1; /* Re-fetch after Register 1 change */
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uint32_t LT :1; /* Re-fetch after LDTLB */
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uint32_t MT :1; /* Re-fetch after writing TLB */
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uint32_t MC :1; /* Re-fetch after writing insn cache */
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);
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} GPACKED(4) sh7305_mmu_t;
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#define SH7305_MMU (*(sh7305_mmu_t *)0xff000000)
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_MMU */
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