274 lines
7.4 KiB
C
274 lines
7.4 KiB
C
//---
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// gint:cpg:overclock - Clock speed control
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//
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// Most of the data in this file has been reused from Sentaro21's Ftune and
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// Ptune utilities, which have long been the standard for overclocking CASIO
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// calculators.
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// See: http://pm.matrix.jp/ftune2e.html
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//
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// SlyVTT also contributed early testing on both the fx-CG 10/20 and fx-CG 50.
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//---
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#include <gint/clock.h>
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#include <gint/gint.h>
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#include <gint/hardware.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/bsc.h>
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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//---
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// Low-level clock speed access
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//---
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#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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void cpg_get_overclock_setting(struct cpg_overclock_setting *s)
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{
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if(!isSH4())
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return;
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s->FLLFRQ = CPG.FLLFRQ.lword;
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s->FRQCR = CPG.FRQCR.lword;
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s->CS0BCR = BSC.CS0BCR.lword;
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s->CS0WCR = BSC.CS0WCR.lword;
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s->CS2BCR = BSC.CS2BCR.lword;
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s->CS2WCR = BSC.CS2WCR.lword;
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s->CS3BCR = BSC.CS3BCR.lword;
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s->CS3WCR = BSC.CS3WCR.lword;
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s->CS5aBCR = BSC.CS5ABCR.lword;
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s->CS5aWCR = BSC.CS5AWCR.lword;
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}
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void cpg_set_overclock_setting(struct cpg_overclock_setting const *s)
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{
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if(!isSH4())
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return;
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BSC.CS0WCR.WR = 11; /* 18 cycles */
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CPG.FLLFRQ.lword = s->FLLFRQ;
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CPG.FRQCR.lword = s->FRQCR;
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CPG.FRQCR.KICK = 1;
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while(CPG.LSTATS != 0) {}
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BSC.CS0BCR.lword = s->CS0BCR;
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BSC.CS0WCR.lword = s->CS0WCR;
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BSC.CS2BCR.lword = s->CS2BCR;
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BSC.CS2WCR.lword = s->CS2WCR;
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BSC.CS3BCR.lword = s->CS3BCR;
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BSC.CS3WCR.lword = s->CS3WCR;
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if(BSC.CS3WCR.A3CL == 1)
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*SDMR3_CL2 = 0;
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else
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*SDMR3_CL3 = 0;
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BSC.CS5ABCR.lword = s->CS5aBCR;
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BSC.CS5AWCR.lword = s->CS5aWCR;
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}
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//---
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// Predefined clock speeds
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//---
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#ifdef FXCG50
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#define PLL_32x 0b011111
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#define PLL_26x 0b011001
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#define PLL_16x 0b001111
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#define DIV_2 0
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#define DIV_4 1
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#define DIV_8 2
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#define DIV_16 3
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#define DIV_32 4
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static struct cpg_overclock_setting settings_cg50[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F011112,
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.CS0BCR = 0x36DA0400,
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.CS2BCR = 0x36DA3400,
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.CS3BCR = 0x36DB4400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000340,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000240,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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};
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static struct cpg_overclock_setting settings_cg20[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F102203,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000001C0,
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.CS2WCR = 0x00000140,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_8<<20)+(DIV_16<<12)+(DIV_16<<8)+DIV_32,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x000100C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_32,
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.CS0BCR = 0x24900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000201C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_32,
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.CS0BCR = 0x44900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x00040340,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_16,
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.CS0BCR = 0x34900400,
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.CS2BCR = 0x04903400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000402C0,
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.CS3WCR = 0x000024D0,
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.CS5aWCR = 0x00010240 },
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};
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static struct cpg_overclock_setting *get_settings(void)
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{
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if(gint[HWCALC] == HWCALC_FXCG50)
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return settings_cg50;
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if(gint[HWCALC] == HWCALC_PRIZM)
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return settings_cg20;
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return NULL;
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}
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int clock_get_speed(void)
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{
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struct cpg_overclock_setting *settings = get_settings();
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if(!settings)
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return CLOCK_SPEED_UNKNOWN;
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for(int i = 0; i < 5; i++) {
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struct cpg_overclock_setting *s = &settings[i];
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if(CPG.FLLFRQ.lword == s->FLLFRQ
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&& CPG.FRQCR.lword == s->FRQCR
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&& BSC.CS0BCR.lword == s->CS0BCR
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&& BSC.CS2BCR.lword == s->CS2BCR
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&& BSC.CS3BCR.lword == s->CS3BCR
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&& BSC.CS5ABCR.lword == s->CS5aBCR
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&& BSC.CS0WCR.lword == s->CS0WCR
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&& BSC.CS2WCR.lword == s->CS2WCR
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&& BSC.CS3WCR.lword == s->CS3WCR
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&& BSC.CS5AWCR.lword == s->CS5aWCR)
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return CLOCK_SPEED_F1 + i;
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}
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return CLOCK_SPEED_UNKNOWN;
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}
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void clock_set_speed(int level)
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{
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if(level < CLOCK_SPEED_F1 || level > CLOCK_SPEED_F5)
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return;
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if(clock_get_speed() == level)
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return;
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struct cpg_overclock_setting *settings = get_settings();
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if(!settings)
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return;
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struct cpg_overclock_setting *s = &settings[level - CLOCK_SPEED_F1];
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uint32_t old_Pphi = clock_freq()->Pphi_f;
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/* Wait for asynchronous tasks to complete */
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gint_world_sync();
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/* Disable interrupts during the change */
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cpu_atomic_start();
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/* Set the clock settings */
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cpg_set_overclock_setting(s);
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/* Determine the change in frequency for Pϕ and recompute CPG data */
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cpg_compute_freq();
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uint32_t new_Pphi = clock_freq()->Pphi_f;
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/* Update timers' TCNT and TCOR to match the new clock speed */
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void timer_rescale(uint32_t old_Pphi, uint32_t new_Pphi);
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timer_rescale(old_Pphi, new_Pphi);
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cpu_atomic_end();
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}
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#endif
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