275 lines
6.6 KiB
C
275 lines
6.6 KiB
C
#include <gint/hardware.h>
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#include <gint/mpu/dma.h>
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#include <gint/mpu/power.h>
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#include <gint/mpu/intc.h>
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#include <gint/gint.h>
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#include <gint/dma.h>
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#include <gint/drivers.h>
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#include <gint/clock.h>
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#include <gint/display.h>
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#include <gint/exc.h>
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#define DMA SH7305_DMA
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#define INTC SH7305_INTC
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#define POWER SH7305_POWER
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typedef volatile sh7305_dma_channel_t channel_t;
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/* dma_channel(): Get address of a DMA channel */
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static channel_t *dma_channel(int channel)
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{
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channel_t *addr[6] = {
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&DMA.DMA0, &DMA.DMA1, &DMA.DMA2,
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&DMA.DMA3, &DMA.DMA4, &DMA.DMA5,
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};
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return ((uint)channel >= 6 ? NULL : addr[channel]);
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}
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/* dma_translate(): Translate virtual address to DMA-suitable form */
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static uint32_t dma_translate(void const *address)
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{
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uint32_t a = (uint32_t)address;
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/* Preserve RS addresses (as of SH7724 Reference, 11.2.2) */
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if(a >= 0xfd800000 && a < 0xfd800800)
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return a;
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/* Translate virtual addresses to IL memory to physical addresses; the
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same address is used (as of SH7724 Reference, 10.3.3) */
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if(a >= 0xe5200000 && a < 0xe5204000)
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return a;
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/* First additional on-chip memory area (XRAM) */
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if(a >= 0xe5007000 && a < 0xE5009000)
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return a;
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/* Second on-chip memory area (YRAM) */
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if(a >= 0xe5017000 && a < 0xe5019000)
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return a;
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/* Translate P1 and P2 addresses to ROM and RAM to physical form */
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if(a >= 0x80000000 && a < 0xc0000000)
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return a & 0x1fffffff;
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/* By default: I don't know what this is, let's preserve it */
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return a;
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}
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//---
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// Driver interface
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//---
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/* dma_setup(): Setup the DMA in interrupt or no-interrupt mode.
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The first parameters are as for dma_transfer() and dma_transfer_noint(). The
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last parameter indicates whether interrupts should be used.
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Returns non-zero if the DMA is busy or a configuration error occurs. */
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static int dma_setup(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode,
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int interrupts)
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{
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channel_t *ch = dma_channel(channel);
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if(!ch) return 1;
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/* Safety guard: only start a transfer if there's not one running */
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if(ch->CHCR.DE) return 1;
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/* Disable channel and disable the master DMA switch */
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ch->CHCR.DE = 0;
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DMA.OR.DME = 0;
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/* Set DMA source and target address */
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ch->SAR = dma_translate(src);
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ch->DAR = dma_translate(dst);
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/* Set the number of blocks to be transferred */
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ch->TCR = blocks;
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/* Fill in CHCR. Set RS=0100 (auto-request) and the user-provided
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values for TS (transfer size), DM and SM (address modes) */
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ch->CHCR.lword = 0x00000400;
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ch->CHCR.TS_32 = (size >> 2);
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ch->CHCR.TS_10 = (size & 3);
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ch->CHCR.DM = dst_mode;
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ch->CHCR.SM = src_mode;
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ch->CHCR.IE = !!interrupts;
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/* Prepare DMAOR by enabling the master switch and clearing the
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blocking flags. */
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DMA.OR.DME = 1;
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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return 0;
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}
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/* dma_transfer(): Perform a data transfer */
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void dma_transfer(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode)
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{
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if(dma_setup(channel, size, blocks, src, src_mode, dst, dst_mode, 1))
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return;
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/* Enable channel, starting the DMA transfer. */
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channel_t *ch = dma_channel(channel);
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ch->CHCR.DE = 1;
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}
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/* dma_transfer_wait(): Wait for a transfer to finish */
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void dma_transfer_wait(int channel)
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{
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channel_t *ch = dma_channel(channel);
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if(!ch) return;
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/* Wait for the channel to be disabled by the interrupt handler */
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while(ch->CHCR.DE) sleep();
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}
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/* dma_transfer_noint(): Perform a data transfer without interruptions */
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void dma_transfer_noint(int channel, dma_size_t size, uint blocks,
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void const *src, dma_address_t src_mode,
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void *dst, dma_address_t dst_mode)
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{
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if(dma_setup(channel, size, blocks, src, src_mode, dst, dst_mode, 0))
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return;
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/* Enable channel, starting the DMA transfer. */
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channel_t *ch = dma_channel(channel);
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ch->CHCR.DE = 1;
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/* Actively wait until the transfer is finished */
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while(!ch->CHCR.TE);
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/* Disable the channel and clear the TE flag. Disable the channel first
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as clearing the TE flag will allow the transfer to restart */
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ch->CHCR.DE = 0;
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ch->CHCR.TE = 0;
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/* Clear the AE and NMIF status flags */
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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}
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//---
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// Initialization
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//---
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static void init(void)
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{
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/* This driver is not implemented on SH3 */
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if(isSH3()) return;
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/* Install the interrupt handler from dma/inth.s */
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int codes[] = { 0x800, 0x820, 0x840, 0x860, 0xb80, 0xba0 };
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extern void inth_dma_te(void);
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for(int i = 0; i < 6; i++)
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{
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/* Install interrupt handler */
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void *h = gint_inthandler(codes[i], inth_dma_te, 32);
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channel_t *ch = dma_channel(i);
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/* Set its CHCR address */
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*(volatile uint32_t **)(h + 24) = &ch->CHCR.lword;
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/* Clear the enable flag */
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ch->CHCR.DE = 0;
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}
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/* Install the address error gate */
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extern void inth_dma_ae(void);
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gint_inthandler(0xbc0, inth_dma_ae, 32);
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/* Set interrupt priority to 3 (IPRE[15..12] for first three channels,
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IPRF[11..8] for last two and error gate */
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gint_intlevel(16, 3);
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gint_intlevel(21, 3);
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/* Unmask the channel interrupts and the address error */
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INTC.MSKCLR->IMR1 = 0x0f;
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INTC.MSKCLR->IMR5 = 0x70;
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/* Clear blocking flags and enable the master switch */
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DMA.OR.AE = 0;
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DMA.OR.NMIF = 0;
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DMA.OR.DME = 1;
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gint[HWDMA] = HW_LOADED;
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}
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static void unload(void)
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{
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/* Make sure any DMA transfer is finished before leaving the app */
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for(int i = 0; i < 6; i++) dma_transfer_wait(i);
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}
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//---
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// Context system for this driver
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//---
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typedef struct
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{
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channel_t ch[6];
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uint16_t OR;
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int clock;
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} GPACKED(4) ctx_t;
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/* One buffer for the system state will go in gint's .bss section */
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GBSS static ctx_t sys_ctx;
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static void ctx_save(void *buf)
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{
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ctx_t *ctx = buf;
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for(int i = 0; i < 6; i++)
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{
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channel_t *ch = dma_channel(i);
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ctx->ch[i].SAR = ch->SAR;
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ctx->ch[i].DAR = ch->DAR;
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ctx->ch[i].TCR = ch->TCR;
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ctx->ch[i].CHCR.lword = ch->CHCR.lword;
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}
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ctx->OR = DMA.OR.word;
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/* Save the supply status of the DMA0 clock */
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ctx->clock = POWER.MSTPCR0.DMAC0;
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}
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static void ctx_restore(void *buf)
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{
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ctx_t *ctx = buf;
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for(int i = 0; i < 6; i++)
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{
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channel_t *ch = dma_channel(i);
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ch->SAR = ctx->ch[i].SAR;
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ch->DAR = ctx->ch[i].DAR;
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ch->TCR = ctx->ch[i].TCR;
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ch->CHCR.lword = ctx->ch[i].CHCR.lword;
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}
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DMA.OR.word = ctx->OR;
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/* Restore the supply status of the DMA0 clock */
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POWER.MSTPCR0.DMAC0 = ctx->clock;
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}
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//---
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// Driver structure definition
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//---
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gint_driver_t drv_dma0 = {
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.name = "DMA0",
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.init = init,
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.unload = unload,
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.ctx_size = sizeof(ctx_t),
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.sys_ctx = &sys_ctx,
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.ctx_save = ctx_save,
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.ctx_restore = ctx_restore,
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};
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GINT_DECLARE_DRIVER(2, drv_dma0);
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