70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
//---
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// core:cpu - CPU registers and operation management
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//---
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#ifndef GINT_CORE_CPU
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#define GINT_CORE_CPU
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#include <gint/defs/types.h>
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/* cpu_setVBR(): Change VBR address
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Blocks interrupts then changes the VBR address and calls the provided INTC
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configuration function before restoring interrupts. This function must
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configure the INTC in a way that is safe for the new VBR controller,
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including disabling all interrupts that it cannot handle.
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This function is loaded to a platform-dependent address determined at
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runtime; call it indirectly through the function pointer.
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@vbr New VBR address
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@conf_intc Configuration function
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@arg Additional argument for conf_intc
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Returns the previous VBR address. */
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extern uint32_t (*cpu_setVBR)(uint32_t vbr, void (*conf_intc)(int arg),
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int arg);
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/* cpu_getVBR(): Query the current VBR address */
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uint32_t cpu_getVBR(void);
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/* cpu_setCPUOPM(): Change the CPU Operation Mode register
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Updates the CPU Operation Mode with the specified settings, then performs a
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read and an ICBI to register the change. Only writable bits of CPUOPM should
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be changed, other bits must be left at the value given by cpu_getcpuopm().
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@CPUOPM New operation mode */
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void cpu_setCPUOPM(uint32_t CPUOPM);
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/* cpu_getCPUOPM(): Get the CPU OperatioN Mode register */
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uint32_t cpu_getCPUOPM(void);
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//---
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// Status Register
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//---
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/* Status Register bits */
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typedef lword_union(sr_t,
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uint32_t :1;
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uint32_t MD :1;
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uint32_t RB :1;
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uint32_t BL :1;
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uint32_t RC :12;
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uint32_t :3;
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uint32_t DSP :1;
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uint32_t DMY :1;
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uint32_t DMX :1;
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uint32_t M :1;
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uint32_t Q :1;
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uint32_t IMASK :4;
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uint32_t RF :2;
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uint32_t S :1;
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uint32_t T :1;
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);
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/* Get and set sr through the sr_t type */
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sr_t cpu_getSR(void);
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void cpu_setSR(sr_t sr);
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#endif /* GINT_CORE_CPU */
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