71 lines
1.1 KiB
ArmAsm
71 lines
1.1 KiB
ArmAsm
.global _gint_tlbh
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.section .gint.tlbh
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.align 4
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_gint_tlbh:
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get HWMPU in gint's hardware info. If last bit is set, we're SH3 */
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mov.l .gint, r0
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mov.l @r0, r0
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tst #1, r0
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mov.l .tea_sh4, r0
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bt test_tea
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mov.l .tea_sh3, r0
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test_tea:
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/* Check TEA to see if we want to map a page or raise a SysERROR */
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mov.l @r0, r0
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mov.l .max_mapped_rom, r1
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cmp/ge r1, r0
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bt panic
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mov.l .min_mapped_rom, r1
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cmp/ge r1, r0
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bf panic
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map:
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/* If TEA is mappable, map a page and return */
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mov.l .TLB_LoadPTEH, r0
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jsr @r0
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nop
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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panic:
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/* Otherwise, panic by defaulting to the exception handler (the TLB
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miss may still be resolved by a panic handler) */
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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stc vbr, r0
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mov #1, r1
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shll8 r1
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add r1, r0
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jmp @r0
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nop
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.align 4
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.gint:
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.long _gint
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.tea_sh4:
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.long 0xff00000c
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.tea_sh3:
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.long 0xfffffffc
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.min_mapped_rom:
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.long 0x00300000
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.max_mapped_rom:
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.long 0x00300000 + _srom
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.TLB_LoadPTEH:
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.long ___TLB_LoadPTEH
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