253 lines
6.7 KiB
C
253 lines
6.7 KiB
C
#include <gint/intc.h>
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#include <gint/gint.h>
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#include <gint/drivers.h>
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#include <gint/drivers/states.h>
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#include <gint/hardware.h>
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#include <gint/cpu.h>
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#include <gint/mpu/intc.h>
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#include <string.h>
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//---
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// Interrupt controllers
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//---
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GDATA3 sh7705_intc_t SH7705_INTC = {
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.IPR = {
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(void *)0xfffffee2, (void *)0xfffffee4,
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(void *)0xa4000016, (void *)0xa4000018, (void *)0xa400001a,
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(void *)0xa4080000, (void *)0xa4080002, (void *)0xa4080004,
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},
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.ICR1 = (void *)0xa4000010,
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};
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sh7305_intc_t SH7305_INTC = {
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.IPR = (void *)0xa4080000,
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.MSK = (void *)0xa4080080,
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.MSKCLR = (void *)0xa40800c0,
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.USERIMASK = (void *)0xa4700000,
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};
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/* Interrupt IPR and IMR positions. The order of entries is as in the named
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list of interrupt signals in <gint/intc.h>. */
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/* Friendly names for IPR and IMR register numbers */
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enum{ IPRA, IPRB, IPRC, IPRD, IPRE, IPRF, IPRG, IPRH, IPRI, IPRJ, IPRK, IPRL };
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enum{ IMR0, IMR1, IMR2, IMR3, IMR4, IMR5, IMR6, IMR7, IMR8, IMR9, IMR10 };
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#define _ 0,0
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static struct info {
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uint16_t IPR4, IPR4bits, IMR, IMRbits;
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/* Only set if different than IPR4 with IPR4bits */
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uint16_t IPR3, IPR3bits;
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} const info[] = {
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/* Standard TMU */
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{ IPRA, 0xf000, IMR4, 0x10, _ },
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{ IPRA, 0x0f00, IMR4, 0x20, _ },
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{ IPRA, 0x00f0, IMR4, 0x40, _ },
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/* ETMU */
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{ IPRJ, 0xf000, IMR6, 0x08, IPRF, 0x000f },
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{ IPRG, 0x0f00, IMR5, 0x02, _ },
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{ IPRG, 0x00f0, IMR5, 0x04, _ },
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{ IPRE, 0x00f0, IMR2, 0x01, _ },
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{ IPRI, 0xf000, IMR6, 0x10, _ },
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{ IPRL, 0xf000, IMR8, 0x02, _ },
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/* DMA */
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{ IPRE, 0xf000, IMR1, 0x01, _ /* Not supported on SH3! */ },
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{ IPRE, 0xf000, IMR1, 0x02, _ },
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{ IPRE, 0xf000, IMR1, 0x04, _ },
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{ IPRE, 0xf000, IMR1, 0x08, _ },
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{ IPRF, 0x0f00, IMR5, 0x10, _ },
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{ IPRF, 0x0f00, IMR5, 0x20, _ },
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{ IPRF, 0x0f00, IMR5, 0x40, _ },
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/* RTC */
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{ IPRK, 0xf000, IMR10, 0x04, IPRA, 0x000f },
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{ IPRK, 0xf000, IMR10, 0x02, IPRA, 0x000f },
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{ IPRK, 0xf000, IMR10, 0x01, IPRA, 0x000f },
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/* SPU */
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{ IPRC, 0x000f, IMR3, 0x04, _ /* Not supported on SH3! */ },
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{ IPRC, 0x000f, IMR4, 0x08, _ },
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/* USB */
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{ IPRF, 0x00f0, IMR9, 0x02, _ /* Driver not SH3-compatible yet */ },
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};
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/* Compact SH3 VBR-space scheme
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Due to the low amount of memory available on SH3, event codes that are
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translated to SH4 are further remapped into the VBR space to eliminate gaps
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and save space. Each entry in this table represents a 32-byte block after
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the VBR + 0x200. It shows the SH4 event code whose gate is placed on that
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block (some of gint's SH4 event codes are invented to host helper blocks).
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For instance, the 5th block after the entry gate hosts the interrupt handler
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for SH4 event 0x9e0, which is ETMU0 underflow.
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The _inth_remap table in src/kernel/inth.S combines the SH3-SH4 translation
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with the compact translation, hence its entry for 0xf00 (the SH3 event code
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for ETMU0 underflow) is the offset in this table where 0x9e0 (the SH4 event
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code for the same event) is stored, which is 3. */
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static const uint16_t sh3_vbr_map[] = {
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0x400, /* TMU0 underflow */
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0x420, /* TMU1 underflow */
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0x440, /* TMU2 underflow */
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0x9e0, /* ETMU0 underflow */
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0xd00, /* ETMU logic #1 (ETMU4 underflow) */
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1, /* ETMU logic #2 */
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1, /* ETMU logic #3 */
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0xaa0, /* RTC Periodic Interrupt */
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0
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};
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//---
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// Interrupt controller functions
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//---
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int intc_priority(int intname, int level)
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{
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struct info const *i = &info[intname];
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int IPRn = i->IPR4, IPRbits = i->IPR4bits;
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if(isSH3() && i->IPR3bits != 0)
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{
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IPRn = i->IPR3;
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IPRbits = i->IPR3bits;
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}
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/* Bit-shift for the mask */
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int shift = 0;
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while(IPRbits >>= 4) shift += 4;
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uint16_t volatile *IPR;
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IPR = isSH3() ? SH7705_INTC.IPR[IPRn] : &SH7305_INTC.IPR[2*IPRn];
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int oldlevel = (*IPR >> shift) & 0xf;
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*IPR = (*IPR & ~(0xf << shift)) | (level << shift);
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if(isSH4() && level > 0 && i->IMRbits)
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{
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uint8_t volatile *MSKCLR = &SH7305_INTC.MSKCLR->IMR0;
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MSKCLR[4*i->IMR] = i->IMRbits;
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}
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return oldlevel;
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}
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void *intc_handler(int event_code, const void *handler, size_t size)
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{
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void *dest;
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/* Normalize the event code */
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if(event_code < 0x400) return NULL;
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event_code &= ~0x1f;
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/* Prevent writing beyond the end of the VBR space on SH4. Using code
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0xfc0 into the interrupt handler space (which starts 0x540 bytes
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into VBR-reserved memory) would reach byte 0x540 + 0xfc0 - 0x400 =
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0x1100, which is out of gint's reserved VBR area. */
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if(isSH4() && event_code + size > 0xfc0) return NULL;
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/* On SH3, make VBR compact. Use this offset specified in the VBR map
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above to avoid gaps */
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if(isSH3())
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{
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int index = 0;
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while(sh3_vbr_map[index])
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{
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if((int)sh3_vbr_map[index] == event_code) break;
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index++;
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}
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/* This happens if the event has not beed added to the table,
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ie. the compact VBR scheme does not support this code */
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if(!sh3_vbr_map[index]) return NULL;
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dest = (void *)cpu_getVBR() + 0x200 + index * 0x20;
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}
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/* On SH4, just use the code as offset */
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else
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{
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/* 0x40 is the size of the entry gate */
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dest = (void *)cpu_getVBR() + 0x640 + (event_code - 0x400);
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}
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return memcpy(dest, handler, size);
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}
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bool intc_handler_function(int event_code, gint_call_t function)
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{
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/* Install the generic handler */
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extern void intc_generic_handler(void);
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void *h = intc_handler(event_code, intc_generic_handler, 32);
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if(!h) return false;
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/* Copy the call */
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memcpy(h + 8, &function, 20);
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/* Copy the runtime address of gint_inth_callback() */
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*(void **)(h + 28) = gint_inth_callback;
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return true;
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}
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//---
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// State and driver metadata
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//---
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static void configure(void)
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{
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/* Just disable everything, drivers will enable what they support */
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if(isSH3()) for(int i = 0; i < 8; i++)
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*(SH7705_INTC.IPR[i]) = 0x0000;
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else for(int i = 0; i < 12; i++)
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SH7305_INTC.IPR[2 * i] = 0x0000;
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}
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static void hsave(intc_state_t *s)
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{
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if(isSH3())
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{
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for(int i = 0; i < 8; i++)
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s->IPR[i] = *(SH7705_INTC.IPR[i]);
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}
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else
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{
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for(int i = 0; i < 12; i++)
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s->IPR[i] = SH7305_INTC.IPR[2 * i];
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uint8_t *IMR = (void *)SH7305_INTC.MSK;
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for(int i = 0; i < 13; i++, IMR += 4)
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s->MSK[i] = *IMR;
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}
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}
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static void hrestore(intc_state_t const *s)
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{
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if(isSH3())
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{
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for(int i = 0; i < 8; i++)
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*(SH7705_INTC.IPR[i]) = s->IPR[i];
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}
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else
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{
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for(int i = 0; i < 12; i++)
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SH7305_INTC.IPR[2 * i] = s->IPR[i];
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/* Setting masks it a bit more involved than reading them */
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uint8_t *IMCR = (void *)SH7305_INTC.MSKCLR;
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uint8_t *IMR = (void *)SH7305_INTC.MSK;
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for(int i = 0; i < 13; i++, IMR += 4, IMCR += 4)
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{
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*IMCR = 0xff;
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*IMR = s->MSK[i];
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}
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}
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}
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gint_driver_t drv_intc = {
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.name = "INTC",
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.configure = configure,
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.hsave = (void *)hsave,
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.hrestore = (void *)hrestore,
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.state_size = sizeof(intc_state_t),
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};
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GINT_DECLARE_DRIVER(01, drv_intc);
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