290 lines
7.7 KiB
ArmAsm
290 lines
7.7 KiB
ArmAsm
/*
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** gint:core:inth - Interrupt handlers
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** This file only contains the entry points because the gates are managed
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** by device drivers. Each driver will supply its own interrupt handler
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** blocks depending on its configuration.
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*/
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#define CPP_ASM
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#include <gint/hardware.h>
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.global _gint_inth_7305
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#ifdef FX9860G
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.global _gint_inth_7705
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#endif
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.global _gint_inth_callback
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.section .gint.blocks, "ax"
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.align 4
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/* Interrupt handlers
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The .gint.blocks section consists of blocks of 32 bytes intended for mapping
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into the VBR space (exception, TLB miss, and interrupt handlers). Each event
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gate is linearly associated with a block number on SH4:
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block_id = (event_code - 0x3c0) / 0x20
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and associated with a compact block number on SH3 through a table (to ensure
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that blocks are consecutive in memory).
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This file provides entry points; drivers may provide their own interrupt
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handlers, and store them in the .gint.blocks section for consistency. They
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should be aware of the consequences of reordering the blocks into the VBR
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space:
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- It is possible to map MPU-specific blocks at runtime, to avoid checking
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the MPU each time an interrupt is handled;
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- However, the blocks can only rely on relative displacements or cross-
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references if their relative order is known and heeded for both on SH4 and
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SH3. A good example of this is the timer driver. Please be careful. */
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/* SH7305-TYPE DEBUG INTERRUPT HANDLER - 26 BYTES */
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#if 0
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_gint_inth_7305:
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mov.l 1f, r0
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mov.l @r0, r4
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sts.l pr, @-r15
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mov.l 2f, r0
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jsr @r0
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nop
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lds.l @r15+, pr
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rte
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nop
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.zero 6
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2: .long _debug
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1: .long 0xff000028
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#endif
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/* SH7305-TYPE INTERRUPT HANDLER ENTRY - 40 BYTES */
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_gint_inth_7305:
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/* Save caller-saved registers which might currently be in use by the
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interrupted function, as we don't know what the callback will do */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT register */
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mov.l 1f, r0
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mov.l @r0, r0
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/* Interrupt codes start at 0x400 */
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mov #4, r1
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shll8 r1
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sub r1, r0
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/* Add the distance to the first entry and jump as a subroutine */
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add #(.first_entry - .jump_over), r0
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bsrf r0
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nop
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.jump_over:
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/* Restore caller-saved registers */
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 24
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1: .long 0xff000028
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.first_entry:
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#ifdef FX9860G
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/* SH7705-TYPE INTERRUPT HANDLER ENTRY - 56 BYTES */
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_gint_inth_7705:
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/* Save caller-saved registers as before */
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sts.l pr, @-r15
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stc.l gbr, @-r15
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sts.l mach, @-r15
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sts.l macl, @-r15
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/* Get the event code from the INTEVT2 register */
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mov.l 1f, r0
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mov.l @r0, r0 /* r0 = old_code */
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/* Translate the event code to compact format. The compact format is
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laid out in a way that leaves no gap in the VBR space. Additionally,
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gates are installed starting at VBR + 0x200 to save space. */
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mov.l 2f, r2
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mov #-5, r3
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shld r3, r0 /* r0 = old_code >> 5 */
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add #-32, r0 /* r0 = (old_code - 0x400) >> 5 */
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mov.b @(r0, r2), r0 /* r0 = gate_number */
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add #16, r0 /* r0 = (0x200 + gate_number * 0x20) >> 5 */
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mov #5, r3
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shld r3, r0 /* r0 = 0x200 + gate_number * 0x20 */
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/* Start at VBR + 0x200 and jump! */
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stc vbr, r1
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add r1, r0
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jsr @r0
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nop
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/* Restore saved registers */
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lds.l @r15+, macl
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lds.l @r15+, mach
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ldc.l @r15+, gbr
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lds.l @r15+, pr
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rte
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nop
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.zero 8
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1: .long 0xa4000000 /* INTEVT2 register */
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2: .long _inth_remap
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.data
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.align 4
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/* EVENT CODE TRANSLATION TABLE - 96 BYTES
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This table was originally used to translate SH3 event codes to corresponding
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SH4 events codes so that the VBR can be laid out in the SH4 model on every
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platform. However, due to memory size limitations on SH3, it now also
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translates SH4 event codes to adjacent gates numbers to reduce the size of
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the VBR section.
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The VBR interrupt space on SH3 is laid out as follows:
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VBR offset SH3 events Description
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-------------------------------------------------------------------
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0x200 400 420 440 TMU0, TMU1, TMU2
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0x260 f00 --- --- --- ETMU0, 3-gate logic at ETMU4
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0x2e0 4a0 RTC Periodic Interrupt
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-------------------------------------------------------------------
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0x600 --- --- Entry gate
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-------------------------------------------------------------------
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There is space for 16 gates at VBR + 0x200 so the VBR currently ends after
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the interrupt entry gate at VBR + 0x640. */
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_inth_remap:
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.byte 0, 1, 2, 0xff, 0xff, 7, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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.byte 3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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#endif
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.section .gint.mapped, "ax"
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/* CALLBACK HELPER
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This function implements the callback with context saving. It is a general
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function and does not need to reside in VBR space which is block-structured.
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This function saves registers r0_bank...r7_bank, enables interrupts,
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switches back to user bank and executes the callback. It does not save other
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registers (pr/mach/macl/gbr) which are managed by the handler entry. */
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/* gint_inth_callback: Indirect call from kernel space to userland
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@r4 Address of callback function
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-> Returns the return value of the callback (int). */
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_gint_inth_callback_reloc:
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stc.l r0_bank, @-r15
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stc.l r1_bank, @-r15
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stc.l r2_bank, @-r15
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stc.l r3_bank, @-r15
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stc.l r4_bank, @-r15
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stc.l r5_bank, @-r15
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stc.l r6_bank, @-r15
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stc.l r7_bank, @-r15
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stc.l spc, @-r15
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stc.l ssr, @-r15
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stc.l sr, @-r15
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/* Save some values to user bank; once we enable interrupts, the kernel
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bank might be overwritten at any moment. */
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ldc r4, r0_bank
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/* Enable interrupts and go back to user bank. On SH4, SR.IMASK is set
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to the level of the current interrupt, which makes sure we can only
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be re-interrupted by something with a higher priority. */
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stc sr, r1
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mov.l .SR_clear_RB_BL, r0
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and r0, r1
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/* On SH3 the CPUOPM.INTMU bit is not supported, and on the fx-CG
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emulator, it is outright ignored. In these situations, set IMASK to
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15 to block interrupts while allowing TLB misses to be handled. */
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mov.l .gint, r2
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mov.l @r2, r0
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tst #1, r0
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bf .set_imask
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mov.l @(4*HWCALC,r2), r0
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cmp/eq #HWCALC_FXCG_MANAGER, r0
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bt .set_imask
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bra .load_sr
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nop
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.set_imask:
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mov.l .SR_set_IMASK, r0
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or r0, r1
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.load_sr:
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ldc r1, sr
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/* We are now in the user bank with r0 set. Perform the call. We want
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to forward the return value to kernel bank, but this bank can be
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changed at any moment since interrupts are enabled. */
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sts.l pr, @-r15
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mov.l @(4, r0), r4
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mov.l @(8, r0), r5
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mov.l @(12, r0), r6
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mov.l @(16, r0), r7
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mov.l @r0, r0
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jsr @r0
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nop
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lds.l @r15+, pr
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/* Restore the previous status register and the registers of the
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interrupted procedure. Restoring sr gets us back to system bank with
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interrupts disabled. */
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ldc.l @r15+, sr
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/* We can now pull the return value since interrupts are disabled */
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stc r0_bank, r0
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ldc.l @r15+, ssr
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ldc.l @r15+, spc
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ldc.l @r15+, r7_bank
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ldc.l @r15+, r6_bank
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ldc.l @r15+, r5_bank
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ldc.l @r15+, r4_bank
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ldc.l @r15+, r3_bank
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ldc.l @r15+, r2_bank
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ldc.l @r15+, r1_bank
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rts
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ldc.l @r15+, r0_bank
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.align 4
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.SR_clear_RB_BL:
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.long ~((1 << 29) | (1 << 28))
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.SR_set_IMASK:
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.long (0xf << 4)
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.gint:
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.long _gint
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.section .gint.mappedrel, "aw"
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_gint_inth_callback:
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.long _gint_inth_callback_reloc
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