90 lines
1.7 KiB
ArmAsm
90 lines
1.7 KiB
ArmAsm
.global _ubc_setDBR
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.global _ubc_getDBR
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.text
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_ubc_setDBR:
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ldc r4, dbr
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rts
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nop
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_ubc_getDBR:
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stc dbr, r0
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rts
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nop
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.global _ubc_dbh
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_ubc_dbh:
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/* We backup registers in the correct order to build gdb_cpu_state_t */
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stc.l ssr, @-r15
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sts.l macl, @-r15
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sts.l mach, @-r15
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stc.l vbr, @-r15
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stc.l gbr, @-r15
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sts.l pr, @-r15
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stc.l spc, @-r15
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stc.l sgr, @-r15
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mov.l r14, @-r15
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mov.l r13, @-r15
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mov.l r12, @-r15
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mov.l r11, @-r15
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mov.l r10, @-r15
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mov.l r9, @-r15
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mov.l r8, @-r15
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stc.l R7_BANK, @-r15
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stc.l R6_BANK, @-r15
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stc.l R5_BANK, @-r15
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stc.l R4_BANK, @-r15
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stc.l R3_BANK, @-r15
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stc.l R2_BANK, @-r15
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stc.l R1_BANK, @-r15
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stc.l R0_BANK, @-r15
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/* Enable interrupts and switch register bank
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Original SR is kept in r8 */
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stc sr, r8
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mov r8, r1
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mov.l .sr_mask, r0
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and r0, r1
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ldc r1, sr
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mov r15, r4
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mov.l .handler, r0
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jsr @r0
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nop
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/* Restore original SR to access the correct register bank */
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ldc r8, sr
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ldc.l @r15+, R0_BANK
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ldc.l @r15+, R1_BANK
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ldc.l @r15+, R2_BANK
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ldc.l @r15+, R3_BANK
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ldc.l @r15+, R4_BANK
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ldc.l @r15+, R5_BANK
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ldc.l @r15+, R6_BANK
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ldc.l @r15+, R7_BANK
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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ldc.l @r15+, sgr
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ldc.l @r15+, spc
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lds.l @r15+, pr
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ldc.l @r15+, gbr
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ldc.l @r15+, vbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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ldc.l @r15+, ssr
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rte
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nop
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.align 4
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.handler: .long _ubc_debug_handler
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.sr_mask: .long ~0x300000f0 /* IMASK = 0 : mask no interrupts
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BL = 0 : do not block interrupts
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RB = 0 : use register BANK0
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*/
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