135 lines
2.8 KiB
C
135 lines
2.8 KiB
C
//---
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// gint:mpu:cpg - Clock Pulse Generator
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//---
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#ifndef GINT_MPU_CPG
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#define GINT_MPU_CPG
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 Clock Pulse Generator. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 9: "Interrupt Controller (INTC)"
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//---
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/* sh7705_cpg_t - Clock Pulse Generator registers */
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typedef volatile struct
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{
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word_union(FRQCR,
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uint16_t :3;
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uint16_t CKOEN :1; /* Clock Output Enable */
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uint16_t :2;
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uint16_t STC :2; /* PLL multiplication ratio */
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uint16_t :2;
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uint16_t IFC :2; /* Internal clock divider */
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uint16_t :2;
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uint16_t PFC :2; /* Peripheral clock divider */
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);
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} GPACKED(4) sh7705_cpg_t;
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#define SH7705_CPG (*((sh7705_cpg_t *)0xffffff80))
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//---
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// SH7305 Clock Pulse Generator. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 17: "Clock Pulse Generator (CPG)"
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//---
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/* sh7305_cpg_t - Clock Pulse Generator registers
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Fields marked with [*] don't have the meaning described in the SH7724
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documentation. */
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typedef volatile struct
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{
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lword_union(FRQCRA,
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uint32_t KICK :1; /* Flush FRQCRA modifications */
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uint32_t :1;
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uint32_t STC :6; /* PLL multiplication [*] */
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uint32_t IFC :4; /* Iphi divider 1 [*] */
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uint32_t :4;
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uint32_t SFC :4; /* Sphi divider 1 [*] */
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uint32_t BFC :4; /* Bphi divider 1 [*] */
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uint32_t :4;
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uint32_t P1FC :4; /* Pphi divider 1 [*] */
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);
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pad(0x4);
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lword_union(FSICLKCR,
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uint32_t :16;
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uint32_t DIVB :6; /* Division ratio for port B */
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uint32_t :1;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t SRC :2; /* Clock source select */
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uint32_t DIVA :6; /* Division ratio for port A */
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);
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pad(0x04);
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lword_union(DDCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t _ :1; /* Unknown */
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uint32_t :1;
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uint32_t DIV :6;
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);
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lword_union(USBCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t :8;
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);
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pad(0x0c);
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lword_union(PLLCR,
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uint32_t :17;
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uint32_t PLLE :1; /* PLL Enable */
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uint32_t :1;
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uint32_t FLLE :1; /* FLL Enable */
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uint32_t :10;
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uint32_t CKOFF :1; /* CKO Output Stop */
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uint32_t :1;
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);
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uint32_t PLL2CR;
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pad(0x10);
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lword_union(SPUCLKCR,
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uint32_t :23;
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uint32_t CLKSTP :1; /* Clock Stop */
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uint32_t _ :1; /* Unknown */
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uint32_t :1;
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uint32_t DIV :6; /* Division ratio */
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);
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pad(0x4);
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lword_union(SSCGCR,
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uint32_t SSEN :1; /* Spread Spectrum Enable */
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uint32_t :31;
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);
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pad(0x8);
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lword_union(FLLFRQ,
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uint32_t :16;
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uint32_t SELXM :2; /* FLL output division */
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uint32_t :3;
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uint32_t FLF :11; /* FLL Multiplication Ratio */
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);
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pad(0x0c);
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uint32_t LSTATS;
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} GPACKED(4) sh7305_cpg_t;
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#define SH7305_CPG (*((sh7305_cpg_t *)0xa4150000))
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_CPG */
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