225 lines
4.8 KiB
C
225 lines
4.8 KiB
C
//---
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// gint:mpu:bsc - Bus State Controller
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//---
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#ifndef GINT_MPU_BSC
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#define GINT_MPU_BSC
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 But State Controller. Refer to:
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// Renesas SH7705 Group Hardware Manual
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// Section 7: Bus State Controller (BSC)
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//---
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typedef volatile lword_union(sh7705_bsc_CSnBCR_t,
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uint32_t :2;
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uint32_t IWW :2; /* Wait cycles for Write-Read and Write-Write */
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uint32_t :1;
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uint32_t IWRWD :2; /* Wait cycles for other-space Read-Write */
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uint32_t :1;
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uint32_t IWRWS :2; /* Wait cycles for same-space Read-Write */
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uint32_t :1;
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uint32_t IWRRD :2; /* Wait cycles for other-space Read-Read */
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uint32_t :1;
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uint32_t IWRRS :2; /* Wait cycles for same-space Read-Read */
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uint32_t :1;
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uint32_t TYPE :3; /* Memory type */
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uint32_t :1;
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uint32_t BSZ :2; /* Data bus size */
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uint32_t :9;
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);
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/* Warning: the layout of this register changes with n *and* with the memory
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type. This version is not exhaustive. Check the manual! */
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typedef volatile lword_union(sh7705_bsc_CSnWCR_t,
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uint32_t :13;
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uint32_t WW :3; /* Write access wait cycles */
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uint32_t :3;
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uint32_t SW :2; /* Wait from CSn/address to RD/WEn assertion */
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uint32_t WR :4; /* Access wait cycles */
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uint32_t WM :1; /* Whether to use external wait */
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uint32_t :4;
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uint32_t HW :2; /* Wait from RD/WEn to CSn/address negation */
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);
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typedef volatile struct
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{
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lword_union(CMNCR,
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uint32_t :24;
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uint32_t DMAIW :2; /* DMA single-address wait states */
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uint32_t DMAIWA :1; /* DMAIW wait states insertion method */
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uint32_t :1;
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uint32_t const ENDIAN :1; /* Global CPU endianness flag */
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uint32_t :1;
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uint32_t HIZMEM :1; /* High-Z memory Control*/
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uint32_t HIZCNT :1; /* High-Z Control*/
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);
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sh7705_bsc_CSnBCR_t CS0BCR;
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sh7705_bsc_CSnBCR_t CS2BCR;
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sh7705_bsc_CSnBCR_t CS3BCR;
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sh7705_bsc_CSnBCR_t CS4BCR;
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sh7705_bsc_CSnBCR_t CS5ABCR;
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sh7705_bsc_CSnBCR_t CS5BBCR;
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sh7705_bsc_CSnBCR_t CS6ABCR;
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sh7705_bsc_CSnBCR_t CS6BBCR;
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sh7705_bsc_CSnWCR_t CS0WCR;
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sh7705_bsc_CSnWCR_t CS2WCR;
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sh7705_bsc_CSnWCR_t CS3WCR;
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sh7705_bsc_CSnWCR_t CS4WCR;
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sh7705_bsc_CSnWCR_t CS5AWCR;
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sh7705_bsc_CSnWCR_t CS5BWCR;
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sh7705_bsc_CSnWCR_t CS6AWCR;
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sh7705_bsc_CSnWCR_t CS6BWCR;
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/* TODO: There are more registers (not involved in overclocking). */
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} GPACKED(4) sh7705_bsc_t;
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#define SH7705_BSC (*(sh7705_bsc_t *)0xa4fd0000)
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//---
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// SH7305 But State Controller. Refer to:
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// Renesas SH7730 Group Hardware Manual
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// Section 11: Bus State Controller (BSC)
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//---
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typedef volatile lword_union(sh7305_bsc_CSnBCR_t,
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uint32_t :1;
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uint32_t IWW :3;
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uint32_t IWRWD :3;
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uint32_t IWRWS :3;
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uint32_t IWRRD :3;
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uint32_t IWRRS :3;
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uint32_t TYPE :4;
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uint32_t :1;
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uint32_t BSZ :2;
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uint32_t :9;
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);
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typedef volatile lword_union(sh7305_bsc_CSnWCR_06A6B_t,
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uint32_t :11;
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uint32_t BAS :1;
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uint32_t :1;
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uint32_t WW :3;
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uint32_t ADRSFIX:1;
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uint32_t :2;
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uint32_t SW :2;
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uint32_t WR :4;
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uint32_t WM :1;
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uint32_t :4;
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uint32_t HW :2;
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);
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typedef volatile lword_union(sh7305_bsc_CSnWCR_45A5B_t,
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uint32_t :11;
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uint32_t BAS :1;
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uint32_t :1;
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uint32_t WW :3;
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uint32_t :3;
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uint32_t SW :2;
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uint32_t WR :4;
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uint32_t WM :1;
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uint32_t :4;
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uint32_t HW :2;
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);
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typedef volatile struct
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{
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lword_union(CMNCR,
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uint32_t :6;
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uint32_t CKOSTP :1;
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uint32_t CKODRV :1;
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uint32_t :7;
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uint32_t DMSTP :1;
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uint32_t :1;
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uint32_t BSD :1;
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uint32_t MAP :2;
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uint32_t BLOCK :1;
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uint32_t :7;
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uint32_t ENDIAN :1;
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uint32_t :1;
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uint32_t HIZMEM :1;
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uint32_t HIZCNT :1;
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);
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sh7305_bsc_CSnBCR_t CS0BCR;
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sh7305_bsc_CSnBCR_t CS2BCR;
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sh7305_bsc_CSnBCR_t CS3BCR;
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sh7305_bsc_CSnBCR_t CS4BCR;
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sh7305_bsc_CSnBCR_t CS5ABCR;
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sh7305_bsc_CSnBCR_t CS5BBCR;
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sh7305_bsc_CSnBCR_t CS6ABCR;
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sh7305_bsc_CSnBCR_t CS6BBCR;
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sh7305_bsc_CSnWCR_06A6B_t CS0WCR;
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lword_union(CS2WCR,
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uint32_t :8;
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uint32_t BW :2;
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uint32_t PMD :1;
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uint32_t BAS :1;
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uint32_t :1;
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uint32_t WW :3;
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uint32_t :3;
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uint32_t SW :2;
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uint32_t WR :4;
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uint32_t WM :1;
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uint32_t :4;
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uint32_t HW :2;
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);
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lword_union(CS3WCR,
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uint32_t :17;
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uint32_t TRP :2;
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uint32_t :1;
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uint32_t TRCD :2;
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uint32_t :1;
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uint32_t A3CL :2;
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uint32_t :2;
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uint32_t TRWL :2;
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uint32_t :1;
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uint32_t TRC :2;
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);
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sh7305_bsc_CSnWCR_45A5B_t CS4WCR;
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sh7305_bsc_CSnWCR_45A5B_t CS5AWCR;
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sh7305_bsc_CSnWCR_45A5B_t CS5BWCR;
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sh7305_bsc_CSnWCR_06A6B_t CS6AWCR;
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sh7305_bsc_CSnWCR_06A6B_t CS6BWCR;
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lword_union(SDCR,
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uint32_t :11;
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uint32_t A2ROW :2;
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uint32_t :1;
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uint32_t A2COL :2;
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uint32_t :4;
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uint32_t RFSH :1;
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uint32_t RMODE :1;
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uint32_t PDOWN :1;
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uint32_t BACTV :1;
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uint32_t :3;
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uint32_t A3ROW :2;
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uint32_t :1;
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uint32_t A3COL :2;
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);
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uint32_t RTCSR;
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uint32_t RTCNT;
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uint32_t RTCOR;
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} GPACKED(4) sh7305_bsc_t;
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#define SH7305_BSC (*(sh7305_bsc_t *)0xfec10000)
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_BSC */
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