155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
//---
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// gint:clock:freq - Clock frequency management
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//---
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#include <gint/drivers.h>
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#include <gint/drivers/states.h>
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#include <gint/clock.h>
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#include <gint/hardware.h>
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#include <gint/mpu/cpg.h>
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//---
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// Driver storage
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//---
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/* Local copy of the CPG settings */
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GBSS static clock_frequency_t freq;
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/* clock_freq() - get the frequency of the main clocks */
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const clock_frequency_t *clock_freq(void)
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{
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return &freq;
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}
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//---
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// SH7705 Clock signals
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//---
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#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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void sh7705_probe(void)
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{
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/* According to Sentaro21 in the sources of Ftune 1.0.1, the clock mode
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is thought to be 5, which means that:
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- CPG input is XTAL (14.745'600 MHz)
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- PLL2 is active and *2 (29.491'200 MHz)
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- CKIO is output from PLL2 (29.491'200 MHz) */
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int xtal = 14745600;
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int pll2 = 2;
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int ckio = xtal * pll2;
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/* This signal is multiplied by the PLL1 circuit */
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int pll1 = SH7705_CPG.FRQCR.STC + 1;
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/* Fill in the setting structure. Iϕ and Pϕ have dividers, while Bϕ is
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always equal to CKIO. */
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freq.PLL1 = pll1;
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freq.PLL2 = pll2;
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freq.Bphi_div = 1;
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freq.Iphi_div = SH7705_CPG.FRQCR.IFC + 1;
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freq.Pphi_div = SH7705_CPG.FRQCR.PFC + 1;
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/* Deduce the frequency of the main clocks */
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freq.CKIO_f = ckio;
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freq.Bphi_f = ckio;
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freq.Iphi_f = (ckio * pll1) / freq.Iphi_div;
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freq.Pphi_f = (ckio * pll1) / freq.Pphi_div;
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}
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#endif /* FX9860G and platform-agnostic */
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//---
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// SH7305 clock signals
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//---
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#define CPG SH7305_CPG
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static void sh7305_probe(void)
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{
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/* The meaning of the PLL setting on SH7305 differs from the
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documentation of SH7224; the value must not be doubled. */
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int pll = CPG.FRQCR.STC + 1;
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freq.PLL = pll;
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/* The FLL ratio is the value of the setting, halved if SELXM=1 */
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int fll = CPG.FLLFRQ.FLF;
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if(CPG.FLLFRQ.SELXM == 1) fll >>= 1;
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freq.FLL = fll;
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/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
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the SH7305 it is 1 / (2^setting + 1). */
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int divb = CPG.FRQCR.BFC;
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int divi = CPG.FRQCR.IFC;
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int divp = CPG.FRQCR.P1FC;
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freq.Bphi_div = 1 << (divb + 1);
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freq.Iphi_div = 1 << (divi + 1);
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freq.Pphi_div = 1 << (divp + 1);
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/* Deduce the input frequency of divider 1 */
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int base = 32768;
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if(CPG.PLLCR.FLLE) base *= fll;
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if(CPG.PLLCR.PLLE) base *= pll;
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/* And the frequency of all other input clocks */
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freq.RTCCLK_f = 32768;
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freq.Bphi_f = base >> (divb + 1);
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freq.Iphi_f = base >> (divi + 1);
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freq.Pphi_f = base >> (divp + 1);
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}
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#undef CPG
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//---
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// Initialization
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//---
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void cpg_compute_freq(void)
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{
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/* This avoids warnings about sh7705_probe() being undefined when
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building for fxcg50 */
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#if defined(FX9860G) || (!defined(FX9860G) && !defined(FXCG50))
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isSH3() ? sh7705_probe() :
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#endif
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sh7305_probe();
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}
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static void configure(void)
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{
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/* Disable spread spectrum in SSGSCR */
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if(isSH4())
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SH7305_CPG.SSCGCR.SSEN = 0;
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cpg_compute_freq();
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}
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//---
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// State and driver metadata
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//---
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static void hsave(cpg_state_t *s)
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{
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if(isSH4())
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s->SSCGCR = SH7305_CPG.SSCGCR.lword;
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cpg_get_overclock_setting(&s->speed);
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}
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static void hrestore(cpg_state_t const *s)
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{
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if(isSH4())
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SH7305_CPG.SSCGCR.lword = s->SSCGCR;
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cpg_set_overclock_setting(&s->speed);
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}
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gint_driver_t drv_cpg = {
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.name = "CPG",
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.configure = configure,
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.hsave = (void *)hsave,
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.hrestore = (void *)hrestore,
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.state_size = sizeof(cpg_state_t),
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};
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GINT_DECLARE_DRIVER(05, drv_cpg);
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