90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
//---
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// gint:mpu:dma - Direct Memory Access control
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//
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// The DMA is a major module on fxcg50 because it is needed to send data
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// to the display at a reasonable speed. On fx9860g, it is very rarely
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// used, if ever.
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//---
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#ifndef GINT_MPU_DMA
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#define GINT_MPU_DMA
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#include <gint/defs/types.h>
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//---
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// SH7305 Direct Memory Access Controller. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 16: "Direct Memory Access Controller (DMAC)"
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//---
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/* sh7305_dma_channel_t - One of the main 6 channels of the DMA
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Note that the many settings are only available on channels 0 to 3 (denoted
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by [0..3]) or on channels 0 and 1 (denoted by [0,1]).
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The documentation is apparently wrong about the placement is TS[3:2], the
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neighboring read-only bit must be swapped before TS[3:2]. */
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typedef volatile struct
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{
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uint32_t SAR;
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uint32_t DAR;
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/* Mind that the 8 upper bits should always be written as 0 */
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uint32_t TCR;
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lword_union(CHCR,
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uint32_t :1;
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uint32_t LCKN :1; /* Bus Right Release Enable */
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uint32_t :2;
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uint32_t RPT :3; /* Repeat setting [0..3] */
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uint32_t DA :1; /* DREQ Asynchronous [0,1] */
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uint32_t DO :1; /* DMA Overrun [0,1] */
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uint32_t :1;
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uint32_t TS_32 :2; /* Transfer Size (upper half) */
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uint32_t HE :1; /* Half-End flag [0..3] */
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uint32_t HIE :1; /* Half-end Interrupt Enable [0..3] */
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uint32_t AM :1; /* Acknowledge mode [0,1] */
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uint32_t AL :1; /* Acknowledge level [0,1] */
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uint32_t DM :2; /* Destination address Mode */
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uint32_t SM :2; /* Source address Mode */
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uint32_t RS :4; /* Resource Select [0,1] */
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uint32_t DL :1; /* DREQ Level [0,1] */
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uint32_t DS :1; /* DREQ Source select[0,1] */
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uint32_t TB :1; /* Transfer Bus Mode */
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uint32_t TS_10 :2; /* Transfer Size (lower half) */
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uint32_t IE :1; /* Interrupt Enable */
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uint32_t TE :1; /* Transfer End flag */
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uint32_t DE :1; /* DMA Enable */
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);
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} GPACKED(4) sh7305_dma_channel_t;
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/* sh7305_dma_t - DMA Controller */
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typedef volatile struct
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{
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sh7305_dma_channel_t DMA0;
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sh7305_dma_channel_t DMA1;
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sh7305_dma_channel_t DMA2;
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sh7305_dma_channel_t DMA3;
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word_union(OR,
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uint16_t CMS :4; /* Cycle steal Mode Select */
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uint16_t :2;
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uint16_t PR :2; /* PRiority mode */
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uint16_t :5;
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uint16_t AE :1; /* Address Error flag */
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uint16_t NMIF :1; /* NMI Flag */
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uint16_t DME :1; /* DMA Master Enable */
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);
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pad(14);
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sh7305_dma_channel_t DMA4;
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sh7305_dma_channel_t DMA5;
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} GPACKED(4) sh7305_dma_t;
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#define SH7305_DMA (*((sh7305_dma_t *)0xfe008020))
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#endif /* GINT_MPU_DMA */
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