84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
#include <gint/mpu/spu.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/power.h>
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#include <gint/drivers.h>
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#include <gint/drivers/states.h>
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#include <gint/clock.h>
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#include <gint/intc.h>
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#define SPU SH7305_SPU
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#define DSP0 SH7305_DSP0
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#define DSP1 SH7305_DSP1
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#define CPG SH7305_CPG
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#define POWER SH7305_POWER
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static void configure(void)
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{
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/* Block SPU interrupts from DSP0, DSP1, and their DMA */
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intc_priority(INTC_SPU_DSP0, 0);
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intc_priority(INTC_SPU_DSP1, 0);
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/* Stop both the SPU and FSI clocks */
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CPG.FSICLKCR.lword = 0x00000103;
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CPG.SPUCLKCR.lword = 0x00000100;
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/* Enable the FSI clock, then the SPU/SPURAM clock */
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CPG.FSICLKCR.CLKSTP = 0;
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CPG.SPUCLKCR.CLKSTP = 0;
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/* Power the clocks through MSTPCR2 */
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POWER.MSTPCR2.FSI_SPU = 0;
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/* Reset the SPU */
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SPU.SPUSRST.RST = 0;
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sleep_us_spin(1000);
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SPU.SPUSRST.RST = 1;
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sleep_us_spin(1000);
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/* Initially give all P memory and X memory to DSP0 */
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SPU.PBANKC0 = 0x1f;
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SPU.PBANKC1 = 0x00;
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SPU.XBANKC0 = 0x7f;
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SPU.XBANKC1 = 0x00;
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/* Perform full DSP resets */
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DSP0.DSPCORERST = 1;
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DSP1.DSPCORERST = 1;
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DSP0.DSPRST = 0;
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DSP1.DSPRST = 0;
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sleep_us_spin(1000);
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}
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int spu_zero(void)
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{
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return 0;
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}
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//---
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// State and driver metadata
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//---
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static void hsave(spu_state_t *s)
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{
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s->PBANKC0 = SPU.PBANKC0;
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s->PBANKC1 = SPU.PBANKC1;
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s->XBANKC0 = SPU.XBANKC0;
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s->XBANKC1 = SPU.XBANKC1;
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}
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static void hrestore(spu_state_t const *s)
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{
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SPU.PBANKC0 = s->PBANKC0;
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SPU.PBANKC1 = s->PBANKC1;
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SPU.XBANKC0 = s->XBANKC0;
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SPU.XBANKC1 = s->XBANKC1;
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}
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gint_driver_t drv_spu = {
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.name = "SPU",
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.configure = configure,
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.hsave = (void *)hsave,
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.hrestore = (void *)hrestore,
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.state_size = sizeof(spu_state_t),
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};
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GINT_DECLARE_DRIVER(16, drv_spu);
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