93 lines
3.0 KiB
C
93 lines
3.0 KiB
C
//---
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// gint:cpu - CPU registers and built-in functions
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//---
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#ifndef GINT_CPU
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#define GINT_CPU
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#include <gint/defs/types.h>
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//---
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// Atomic operations
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//---
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/* cpu_atomic_start(): Enter atomic mode
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This function enters "atomic mode", a mode where distractions to the CPU
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(mainly interrupts) are disabled. This is useful when doing critical
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operations on the hardware, because it ensures that no other code will see
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any intermediate state between the start and end of the atomic mode, thereby
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making the sequence atomic to other code.
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Atomic mode disables interrupts with IMASK=15, however it does not set BL=1
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because exceptions never occur on their own (and it is desirable to have
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panic reports if the atomic code is buggy), and TLB misses are almost always
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desirable. If you want to set BL=1, you can do so with cpu_setSR().
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This function uses a mutex so atomic mode can be started within atomic code;
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every cpu_atomic_start() must be paired with exactly one cpu_atomic_end().
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Entering atomic mode several times does not affect the CPU state, however
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atomic mode will be exited only after all exits have been completed.
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Once atomic mod is exited the original value of IMASK at the first call to
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cpu_atomic_start() is restored. */
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void cpu_atomic_start(void);
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/* cpu_atomic_end(): Exit atomic mode
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There should be exactly one cpu_atomic_end() for each cpu_atomic_start(). */
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void cpu_atomic_end(void);
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//---
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// Access to CPU registers
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//---
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/* Read and write the VBR register */
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uint32_t cpu_getVBR(void);
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void cpu_setVBR(uint32_t VBR);
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/* Read and write the CPU Operation Mode register. After a write, the register
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is re-read and an (icbi) instruction is executed to apply the change. Non-
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writable bits should be left to their initial value during a write. */
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uint32_t cpu_getCPUOPM(void);
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void cpu_setCPUOPM(uint32_t CPUOPM);
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/* cpu_str_t: Bits of the Status Register */
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typedef lword_union(cpu_sr_t,
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uint32_t :1;
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uint32_t MD :1;
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uint32_t RB :1;
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uint32_t BL :1;
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uint32_t RC :12;
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uint32_t :3;
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uint32_t DSP :1;
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uint32_t DMY :1;
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uint32_t DMX :1;
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uint32_t M :1;
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uint32_t Q :1;
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uint32_t IMASK :4;
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uint32_t RF :2;
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uint32_t S :1;
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uint32_t T :1;
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);
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/* Read and write the SR register. When writing, only "permanent" bits are set:
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* MD, RB, BL, DSP, IMASK are set.
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* M, Q, S and T are not set to preserve the behavior of ongoing divisions
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and tests. You can change T with (sett) and (clrt).
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* RC, DMY, DMX and DF are not set: use (setrc), (setdmx), (setdmy), and
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(clrdmxy). DF is preserved for old-style (setrc) loops to work. */
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cpu_sr_t cpu_getSR(void);
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void cpu_setSR(cpu_sr_t sr);
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//---
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// Configuration
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//---
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/* cpu_configure_vbr(): Select the VBR address to be loaded in the driver
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This function can be used before the driver is configure()'d. It sets the
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VBR address that will be used in the next world to be initialized. After a
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configure(), this is reset to 0. */
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void cpu_configure_VBR(uint32_t VBR);
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#endif /* GINT_CPU */
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